GigaDevice Semiconductor GD32F3x0 - System Configuration Registers (SYSCFG)

GD32F3x0 User Manual
31
1.6. System configuration registers (SYSCFG)
SYSCFG base address: 0x4001 0000
1.6.1. System configuration register 0 (SYSCFG_CFG0)
Address offset: 0x00
Reset value: 0x0000 000X (X indicates BOOT_MODE[1:0] may be any value according to
the BOOT0 pin and the BOOT1_n option bit after reset).
This register has to be accessed by word (32-bit).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
PB9_HC
CE
Reserved
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
TIMER16
_DMA_R
MP
TIMER15
_DMA_R
MP
USART0
_RX_DM
A_RMP
USART0
_TX_DM
A_RMP
ADC_DM
A_RMP
Reserved
BOOT_MODE[1:0]
rw
rw
rw
rw
rw
r
Bits
Fields
Descriptions
31:20
Reserved
Must be kept at reset value.
19
PB9_HCCE
PB9 pin high current capability enable
When it is set, the PB9 pin can be used to control an infrared LED directly.
0: High current capability on the PB9 pin is enable.
1: High current capability on the PB9 pin is disabled, and the speed control of the
pin is bypassed.
18:13
Reserved
Must be kept at reset value.
12
TIMER16_DMA_RM
P
TIMER 16 DMA request remapping enable
0: Not remap (TIMER16_CH0 and TIMER16_UP DMA requests are mapped on
DMA channel 0)
1: Remap (TIMER16_CH0 and TIMER16_UP DMA requests are mapped on DMA
channel 1)
11
TIMER15_DMA_RM
P
TIMER 15 DMA request remapping enable
0: Not remap (TIMER15_CH0 and TIMER15_UP DMA requests are mapped on
DMA channel 2)
1: Remap (TIMER15_CH0 and TIMER15_UP DMA requests are mapped on DMA
channel 3)
10
USART0_RX_DMA_
RMP
USART0_RX DMA request remapping enable
0: Not remap (USART0_RX DMA requests are mapped on DMA channel 2)
1: Remap (USART0_RX DMA requests are mapped on DMA channel 4)