GigaDevice Semiconductor GD32F3x0 - Status Register (CTC_STAT)

GD32F3x0 User Manual
112
10: Reserved, equals 0 selected
11: Reserved, equals 0 selected.
27
Reserved
Must be kept at reset value.
26:24
REFPSC[2:0]
Reference signal source prescaler
These bits are set and cleared by software
000: Reference signal not divided
001: Reference signal divided by 2
010: Reference signal divided by 4
011: Reference signal divided by 8
100: Reference signal divided by 16
101: Reference signal divided by 32
110: Reference signal divided by 64
111: Reference signal divided by 128
23:16
CKLIM[7:0]
Clock trim base limit value
These bits are set and cleared by software to define the clock trim base limit value.
These bits used to frequency evaluation and automatically trim process. Please
refer to the. Frequency evaluation and automatically trim process for
detail.
15:0
RLVALUE[15:0]
CTC counter reload value
These bits are set and cleared by software to define the CTC counter reload value.
These bits reload to CTC trim counter when a reference sync pulse received to
start or restart the counter.
5.4.3. Status register (CTC_STAT)
Address offset: 0x08
Reset value: 0x0000 0000
This register has to be accessed by word (32-bit).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
REFCAP[15:0]
r
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
REFDIR
Reserved
TRIM
ERR
REF
MISS
CKERR
Reserved
EREFIF
ERRIF
CKWARN
IF
CKOK
IF
r
r
r
r
r
r
r
r
Bits
Fields
Descriptions
31:16
REFCAP[15:0]
CTC counter capture when reference sync pulse.
When a reference sync pulse occurred, the CTC trim counter value is captured to
REFCAP bits.