GigaDevice Semiconductor GD32F3x0 - Option Byte Status Register (FMC_OBSTAT); Write Protection Register (FMC_WP)

GD32F3x0 User Manual
54
Bits
Fields
Descriptions
31:0
ADDR[31:0]
Flash command address bits
These bits are set by software.
ADDR bits are the address of flash erase command
2.4.7. Option byte status register (FMC_OBSTAT)
Address offset: 0x1C
Reset value: 0xXXXX XX0X
This register has to be accessed by word (32-bit).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
OB_DATA[15:0]
r
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
OB_USER[7:0]
Reserved
PLEVEL[1:0]
OBERR
r
r
r
Bits
Fields
Descriptions
31:16
OB_DATA[15:0]
Store OB_DATA[15:0] of option byte block after system reset
15:8
OB_USER[7:0]
Store OB_USER byte of option byte block after system reset
7:3
Reserved
Must be kept at reset value
2:1
PLEVEL[1:0]
Security Protection level
00: No protection level
01: Protect level low
11: Protect level high
0
OBERR
Option byte read error bit.
This bit is set by hardware when the option byte and its complement byte do not
match, and the option byte set 0xFF.
2.4.8. Write protection register (FMC_WP)
Address offset: 0x20
Reset value: 0x0000 XXXX
This register has to be accessed by word (32-bit).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
OB_WP[15:0]