GigaDevice Semiconductor GD32F3x0 - System Configuration Register 2 (SYSCFG_CFG2)

GD32F3x0 User Manual
37
X100: Reserved
X101: Reserved
X110: Reserved
X111: Reserved
3:0
EXTI12_SS[3:0]
EXTI 12 sources selection
X000: PA12 pin
X001: PB12 pin
X010: PC12 pin
X011: Reserved
X100: Reserved
X101: Reserved
X110: Reserved
X111: Reserved
1.6.6. System configuration register 2 (SYSCFG_CFG2)
Address offset: 0x18
Reset value: 0x0000 0000
This register has to be accessed by word (32-bit).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
SRAM_P
CEF
Reserved
LVD_LOC
K
SRAM_P
ARITY_E
RROR_L
OCK
LOCKUP
_LOCK
rc_w1
rw
rw
rw
Bits
Fields
Descriptions
31:9
Reserved
Must be kept at reset value.
8
SRAM_PCEF
SRAM parity check error flag
This bit is set by hardware when an SRAM parity check error occurs. It is cleared
by software by writing 1.
0: No SRAM parity check error detected
1: SRAM parity check error detected
7:3
Reserved
Must be kept at reset value.
2
LVD_LOCK
LVD lock
This bit is set by software and cleared by a system reset.
0: The LVD interrupt is disconnected from the break input of TIMER0 / 14 / 15 / 16.
LVDEN and LVDT[2:0] in the PMU_CTL register can be programmed.
1: The LVD interrupt is connected from the break input of TIMER0 / 14 / 15 / 16.