GigaDevice Semiconductor GD32F3x0 - RTC Power Saving Mode Management; RTC Interrupts; Table 15-1. RTC Power Saving Mode Management; Table 15-2. RTC Interrupts Control

GD32F3x0 User Manual
233
The OPOL bit in RTC_CTL can configure the polarity of the alarm output which means that
the RTC_ALARM output is the opposite of the corresponding flag bit or not.
15.3.15. RTC power saving mode management
Table 15-1. RTC power saving mode management
Mode
Active in Mode
Exit Mode
Sleep
Yes
RTC Interrupts
Deep-Sleep
Yes: if clock source is LXTAL or IRC40K
RTC Alarm / Tamper Event / Timestamp
Event
Standby
Yes: if clock source is LXTAL or IRC40K
RTC Alarm / Tamper Event / Timestamp
Event
15.3.16. RTC interrupts
All RTC interrupts are connected to the EXTI controller.
Below steps should be followed if you want to use the RTC alarm / tamper / timestamp:
1) Configure and enable the corresponding interrupt line to RTC alarm / tamper /
timestamp event of EXTI and set the rising edge for triggering.
2) Configure and enable the RTC alarm / tamper / timestamp global interrupt.
3) Configure and enable the RTC alarm / tamper / timestamp function.
Table 15-2. RTC interrupts control
Interrupt
Event flag
Control Bit
Exit
Sleep
Exit
Deep-sleep
Exit
Standby
Alarm 0
ALRM0F
ALRM0IE
Y
Y(*)
Y(*)
Timestamp
TSF
TSIE
Y
Y(*)
Y(*)
Tamper 0
TP0F
TPIE
Y
Y(*)
Y(*)
Tamper 1
TP1F
TPIE
Y
Y(*)
Y(*)
*: Only active when RTC clock source is LXTAL or IRC40K.