GigaDevice Semiconductor GD32F3x0 - Configuration Register 0 (RCU_CFG0)

GD32F3x0 User Manual
79
0: Disable the HXTAL Bypass mode
1: Enable the HXTAL Bypass mode in which the HXTAL output clock is equal to the
inputclock.
17
HXTALSTB
External crystal oscillator (HXTAL) clock stabilization flag
Set by hardware to indicate if the HXTAL oscillator is stable and ready for use.
0: HXTAL oscillator is not stable
1: HXTAL oscillator is stable
16
HXTALEN
External High Speed oscillator Enable
Set and reset by software. This bit cannot be reset if the HXTAL clock is used as
the system clock or the PLL input clock. Reset by hardware when entering
Deep-sleep or Standby mode.
0: External 4 ~ 32 MHz crystal oscillator disabled
1: External 4 ~ 32 MHz crystal oscillator enabled
15:8
IRC8MCALIB[7:0]
High Speed Internal Oscillator calibration value register
These bits are load automatically at power on.
7:3
IRC8MADJ[4:0]
High Speed Internal Oscillator clock trim adjust value
These bits are set by software. The trimming value is there bits (IRC8MADJ) added
to the IRC8MCALIB[7:0] bits. The trimming value should trim the IRC8M to 8 MHz
± 1%.
2
Reserved
Must be kept at reset value.
1
IRC8MSTB
IRC8M High Speed Internal Oscillator stabilization Flag
Set by hardware to indicate if the IRC8M oscillator is stable and ready for use.
0: IRC8M oscillator is not stable
1: IRC8M oscillator is stable
0
IRC8MEN
Internal High Speed oscillator Enable
Set and reset by software. This bit cannot be reset if the IRC8M clock is used as
the system clock. Set by hardware when leaving Deep-sleep or Standby mode or
the HXTAL clock is stuck at a low or high state when HXTALCKM is set.
0: Internal 8 MHz RC oscillator disabled
1: Internal 8 MHz RC oscillator enabled
4.3.2. Configuration register 0 (RCU_CFG0)
Address offset: 0x04
Reset value: 0x0000 0000
This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
PLLDV
CKOUTDIV[2:0]
PLLMF[4]
CKOUTSEL[2:0]
USBFSPSC[1:0]
PLLMF[3:0]
PLLPREDV
PLLSEL
rw
rw
rw
rw
rw
rw
rw
rw