GigaDevice Semiconductor GD32F3x0 - AHB Enable Register (RCU_AHBEN)

GD32F3x0 User Manual
89
1: Reset window watchdog timer
10:9
Reserved
Must be kept at reset value
8
TIMER13RST
TIMER13 timer reset
This bit is set and reset by software.
0: No reset
1: Reset TIMER13 TIMER
7:5
Reserved
Must be kept at reset value
4
TIMER5RST
TIMER5 timer reset
This bit is set and reset by software.
0: No reset
1: Reset TIMER5 TIMER
3:2
Reserved
Must be kept at reset value
1
TIMER2RST
TIMER2 timer reset
This bit is set and reset by software.
0: No reset
1: Reset TIMER2 timer
0
TIMER1RST
TIMER1 timer reset
This bit is set and reset by software.
0: No reset
1: Reset TIMER1 timer
4.3.6. AHB enable register (RCU_AHBEN)
Address offset: 0x14
Reset value: 0x0000 0014
This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
TSIEN
Reserved
PFEN
Reserved
PDEN
PCEN
PBEN
PAEN
Reserved
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
. Reserved
USBFSE
N
Reserved
CRCEN
Reserved
FMCSPE
N
Reserved
SRAMSP
EN
Reserved
DMAEN
rw
rw
rw
rw
rw
Bits
Fields
Descriptions
31:25
Reserved
Must be kept at reset value
24
TSIEN
TSI clock enable
This bit is set and reset by software.