GigaDevice Semiconductor GD32F3x0 - APB1 Additional Enable Register (RCU_ADDAPB1 EN)

GD32F3x0 User Manual
103
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
IRC48M
STBIE
Reserved
IRC48M
STBIF
Reserved
rw
r
Bits
Fields
Descriptions
31:23
Reserved
Must be kept at reset value
22
IRC48MSTBIC
Internal 48 MHz RC oscillator Stabilization Interrupt Clear
Write 1 by software to reset the IRC48MSTBIF flag.
0: Not reset IRC48MSTBIF flag
1: Reset IRC48MSTBIF flag
21:15
Reserved
Must be kept at reset value
14
IRC48MSTBIE
Internal 48 MHz RC oscillator Stabilization Interrupt Enable
Set and reset by software to enable/disable the IRC48M stabilization interrupt
0: Disable the IRC48M stabilization interrupt
1: Enable the IRC48M stabilization interrupt
13:7
Reserved
Must be kept at reset value
6
IRC48MSTBIF
IRC48M stabilization interrupt flag
Set by hardware when the Internal 48 MHz RC oscillator clock is stable and the
IRC48MSTBIE bit is set.
Reset by software when setting the IRC48MSTBIC bit.
0: No IRC48M stabilization interrupt generated
1: IRC48M stabilization interrupt generated
5:0
Reserved
Must be kept at reset value
4.3.17. APB1 additional enable register (RCU_ADDAPB1EN)
Address offset: 0xF8
Reset value: 0x0000 0000
This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
CTCEN
Reserved
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
Bits
Fields
Descriptions
31:1
Reserved
Must be kept at reset value