GigaDevice Semiconductor GD32F3x0 - Revision History; Table 24-1. Revision History

GD32F3x0 User Manual
663
24. Revision history
Table 24-1. Revision history
Revision No.
Description
Date
1.0
Initial Release
Jun.6, 2017
2.0
Updated format across the whole document
Jun.1, 2019
2.1
Proofreading
Mar.9, 2020
2.2
1. Add the description of VDDA monitor, refer to Option byte
description.
2. Add the description of VDDA monitor, refer to VDD / VDDA
power domain.
3. VDD / VDDA power domain: “Otherwise, if V
DDA
is different
from V
DD
, V
DDA
must always be higher, but the voltage
difference should not exceed 0.3V.”
4. Add the description of “After ADC is enabled, you need delay
t
SU
time for sampling, the value of t
SU
please refer to the
device datasheet”, refer to ADCON enable.
5. Add the description of Note, refer to Function overview.
6. Modified the max speed to 6.75 MBits/s, refer to
Characteristics.
7. Modified the SMBTYPE bit to SMBSEL bit, refer to SMBus
support。
8. Add Figure 13 2. CMP hysteresis。
9. USB host function: SOF Generate: modified the clock to
12HCLK.
Dec.31, 2020
2.3
1. Modified the description of System configuration register 0
(SYSCFG_CFG0): When PB9_HCCE=0, High current
capability on the PB9 pin is disabled, and the speed control of
the pin is bypassed.
2. Modified Table 1 1. Memory map of GD32F3x0 series: the
SRAM address size range from 20K to 16K.
3. Arm® Cortex®-M4 processor and Figure 1 1. The
structure of the Cortex®-M4 processor: add the description
of FPU.
4. Packet error checking: modified the “In DMA mode, the I2C
will send or check PEC value automatically if PECEN bit is
set.” to “In DMA mode, the I2C will send or check PEC value
automatically if PECEN bit and PECTRANS bit is set.”
May.31, 2021
2.4
1. Option byte programming chapter: delected the description
of 32-bit write operation.
2. Table 14 1. Min/max FWDGT timeout period at 40 kHz
(IRC40K): modified the min/max timeout period.
3. ADC internal channels chapter: modified the data
Dec.31, 2021