GigaDevice Semiconductor GD32F3x0 - Backup Domain Control Register (RCU_BDCTL)

GD32F3x0 User Manual
94
13:12
Reserved
Must be kept at reset value
11
WWDGTEN
Window watchdog timer clock enable
This bit is set and reset by software.
0: Disabled Window watchdog timer clock
1: Enabled Window watchdog timer clock
10:9
Reserved
Must be kept at reset value
8
TIMER13EN
TIMER13 timer clock enable
This bit is set and reset by software.
0: Disabled TIMER13 timer clock
1: Enabled TIMER13 timer clock
7:5
Reserved
Must be kept at reset value
4
TIMER5EN
TIMER5 timer clock enable
This bit is set and reset by software.
0: Disabled TIMER5 timer clock
1: Enabled TIMER5 timer clock
3:2
Reserved
Must be kept at reset value
1
TIMER2EN
TIMER2 timer clock enable
This bit is set and reset by software.
0: Disabled TIMER2 timer clock
1: Enabled TIMER2 timer clock
0
TIMER1EN
TIMER1 timer clock enable
This bit is set and reset by software.
0: Disabled TIMER1 timer clock
1: Enabled TIMER1 timer clock
4.3.9. Backup domain control register (RCU_BDCTL)
Address offset: 0x20
Reset value: 0x0000 0018, reset by Backup domain Reset.
This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit)
Note: The LXTALEN, LXTALBPS, RTCSRC and RTCEN bits of the Backup domain control
register (BDCTL) are only reset after a Backup domain Reset. These bits can be modified
only when the BKPWEN bit in the Power control register (PMU_CTL) has to be set.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
BKPRST
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RTCEN
Reserved
RTCSRC[1:0]
Reserved
LXTALDRI[1:0]
LXTALBPS
LXTALSTB
LXTALEN