GigaDevice Semiconductor GD32F3x0 - Page 95

GD32F3x0 User Manual
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Bits
Fields
Descriptions
31:17
Reserved
Must be kept at reset value
16
BKPRST
Backup domain reset
This bit is set and reset by software.
0: No reset
1: Resets Backup domain
15
RTCEN
RTC clock enable
This bit is set and reset by software.
0: Disabled RTC clock
1: Enabled RTC clock
14:10
Reserved
Must be kept at reset value
9:8
RTCSRC[1:0]
RTC clock entry selection
Set and reset by software to control the RTC clock source.
00: No clock selected
01: CK_LXTAL selected as RTC source clock
10: CK_IRC40K selected as RTC source clock
11: (CK_HXTAL / 32) selected as RTC source clock
7:5
Reserved
Must be kept at reset value
4:3
LXTALDRI[1:0]
LXTAL drive capability
Set and reset by software. Backup domain reset reset this value.
00: Lower driving capability
01: Medium low driving capability
10: Medium high driving capability
11: Higher driving capability (reset value)
Note: The LXTALDRI is not in bypass mode.
2
LXTALBPS
LXTAL bypass mode enable
Set and reset by software.
0: Disable the LXTAL Bypass mode
1: Enable the LXTAL Bypass mode
1
LXTALSTB
External low-speed oscillator stabilization
Set by hardware to indicate if the LXTAL output clock is stable and ready for use.
0: LXTAL is not stable
1: LXTAL is stable
0
LXTALEN
LXTAL enable
Set and reset by software.
0: Disable LXTAL
1: Enable LXTAL