GigaDevice Semiconductor GD32F3x0 - Polynomial Register (CRC_POLY)

GD32F3x0 User Manual
148
Reset value: 0xFFFF FFFF
This register has to be accessed by word (32-bit)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
IDATA[31:16]
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
IDATA[15:0]
rw
Bits
Fields
Descriptions
31:0
IDATA[31:0]
Configurable initial CRC data value
When RST bit in CRC_CTL asserted, CRC_DATA will be programmed to this
value.
8.4.5. Polynomial register (CRC_POLY)
Address offset: 0x14
Reset value: 0x04C1 1DB7
This register has to be accessed by word (32-bit)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
POLY[31:16]
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
POLY[15:0]
rw
Bits
Fields
Descriptions
31:0
POLY[31:0]
User configurable polynomial value
This value is used together with PS[1:0] bits.