GigaDevice Semiconductor GD32F3x0 - Page 93

GD32F3x0 User Manual
93
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
SPI1EN
Reserved
WWDGT
EN
Reserved
TIMER13
EN
Reserved
TIMER5E
N
Reserved
TIMER2E
N
TIMER1E
N
rw
rw
rw
rw
rw
rw
Bits
Fields
Descriptions
31
Reserved
Must be kept at reset value
30
CECEN
HDMI CEC interface clock enable
This bit is set and reset by software.
0: Disabled HDMI CEC interface clock
1: Enabled HDMI CEC interface clock
29
DACEN
DAC interface clock enable
This bit is set and reset by software.
0: Disabled DAC interface clock
1: Enabled DAC interface clock
28
PMUEN
Power interface clock enable
This bit is set and reset by software.
0: Disabled Power interface clock
1: Enabled Power interface clock
27:23
Reserved
Must be kept at reset value
22
I2C1EN
I2C1 clock enable
This bit is set and reset by software.
0: Disabled I2C1 clock
1: Enabled I2C1 clock
21
I2C0EN
I2C0 clock enable
This bit is set and reset by software.
0: Disabled I2C0 clock
1: Enabled I2C0 clock
20:18
Reserved
Must be kept at reset value
17
USART1EN
USART1 clock enable
This bit is set and reset by software.
0: Disabled USART1 clock
1: Enabled USART1 clock
16:15
Reserved
Must be kept at reset value
14
SPI1EN
SPI1 clock enable
This bit is set and reset by software.
0: Disabled SPI1 clock
1: Enabled SPI1 clock