GigaDevice Semiconductor GD32F3x0 - Page 16

GD32F3x0 User Manual
16
Figure 13-1. CMP block diagram of GD32F3x0 series ................................................................. 204
Figure 13-2. CMP hysteresis .............................................................................................................. 205
Figure 14-1. Free watchdog timer block diagram......................................................................... 211
Figure 14-2. Window watchdog timer block diagram .................................................................. 217
Figure 14-3. Window watchdog timer timing diagram ................................................................ 218
Figure 15-1. Block diagram of RTC .................................................................................................. 223
Figure 16-1. Advanced timer block diagram .................................................................................. 252
Figure 16-2. Timing chart of internal clock divided by 1 ............................................................ 253
Figure 16-3. Timing chart of PSC value change from 0 to 2 ...................................................... 254
Figure 16-4. Timing chart of up counting mode, PSC=0/2 ......................................................... 255
Figure 16-5. Timing chart of up counting mode, change TIMERx_CAR on the go .............. 256
Figure 16-6. Timing chart of down counting mode, PSC=0/2 ................................................... 257
Figure 16-7. Timing chart of down counting mode, change TIMERx_CAR on the go ........ 257
Figure 16-8. Timing chart of center-aligned counting mode ..................................................... 259
Figure 16-9. Repetition counter timing chart of center-aligned counting mode .................. 260
Figure 16-10. Repetition counter timing chart of up counting mode ...................................... 260
Figure 16-11. Repetition counter timing chart of down counting mode ................................. 261
Figure 16-12. Channel input capture principle .............................................................................. 262
Figure 16-13. Output-compare under three modes ..................................................................... 264
Figure 16-14. EAPWM timechart ....................................................................................................... 265
Figure 16-15. CAPWM timechart ....................................................................................................... 265
Figure 16-16. Complementary output with dead-time insertion ............................................... 268
Figure 16-17. Output behavior in response to a break(The break high active) .................... 269
Figure 16-18. Counter behavior with CI0FE0 polarity non-inverted in mode 2 .................... 270
Figure 16-19. Counter behavior with CI0FE0 polarity inverted in mode 2 ............................. 270
Figure 16-20. Hall sensor is used to BLDC motor ........................................................................ 271
Figure 16-21. Hall sensor timing between two timers ................................................................. 272
Figure 16-22. Restart mode ................................................................................................................ 273
Figure 16-23. Pause mode .................................................................................................................. 273
Figure 16-24. Event mode ................................................................................................................... 274
Figure 16-25. Single pulse mode TIMERx_CHxCV = 4 TIMERx_CAR=99 ............................... 275
Figure 16-26. TIMER0 Master/Slave mode timer example .......................................................... 275
Figure 16-27. Triggering TIMER0 with enable signal of TIMER1 .............................................. 276
Figure 16-28. Triggering TIMER0 and TIMER1 with TIMER1’s CI0 input ................................ 277
Figure 16-29. General Level 0 timer block diagram ..................................................................... 307
Figure 16-30. Timing chart of internal clock divided by 1 .......................................................... 308
Figure 16-31. Timing chart of PSC value change from 0 to 2.................................................... 309
Figure 16-32. Timing chart of up counting mode, PSC=0/2 ....................................................... 310
Figure 16-33. Timing chart of up counting mode, change TIMERx_CAR on the go. .......... 311
Figure 16-34. Timing chart of down counting mode, PSC=0/2 ................................................. 312
Figure 16-35. Timing chart of down counting mode, change TIMERx_CAR on the go. ..... 312
Figure 16-36. Center-aligned counter timechart ........................................................................... 314
Figure 16-37. Channels input capture principle ........................................................................... 315
Figure 16-38. Output-compare under three modes ..................................................................... 317