GD32F3x0 User Manual
539
(TBE is high) and no transmission sequence is processing in the shift register. When a half
word is written to the SPI_DATA register (TBE goes low), the data is transferred from the
transmission buffer to the shift register (TBE goes high) immediately. At the moment, the
transmission sequence begins.
The data is parallel loaded into the 16-bit shift register, and shifted out serially to the I2S_SD
pin, MSB first. The next data should be written to the SPI_DATA register, when the TBE flag
is high. After a write operation to the SPI_DATA register, the TBE flag goes low. When the
current transmission finishes, the data in the transmission buffer is loaded into the shift
register, and the TBE flag goes back high. Software should write the next audio data into
SPI_DATA register before the current data finishes, otherwise, the audio data transmission
is not continuous.
For all standards except PCM, the I2SCH flag is used to distinguish which channel side the
data to transfer belongs to. The I2SCH flag is refreshed at the moment when the TBE flag
goes high. At the beginning, the I2SCH flag is low, indicating the left channel data should be
written to the SPI_DATA register.
In order to disable I2S, it is mandatory to clear the I2SEN bit after the TBE flag is high and
the TRANS flag is low.
I2S master reception sequence
The RBNE flag is used to control the reception sequence. As is mentioned before, the RBNE
flag indicates the reception buffer is not empty, and an interrupt will be generated if the
RBNEIE bit in the SPI_CTL1 register is set. The reception sequence begins immediately
when the I2SEN bit in the SPI_I2SCTL register is set. At the beginning, the reception buffer
is empty (RBNE is low). When a reception sequence finishes, the received data in the shift
register is loaded into the reception buffer (RBNE goes high). The data should be read from
the SPI_DATA register, when the RBNE flag is high. After a read operation to the SPI_DATA
register, the RBNE flag goes low. It is mandatory to read the SPI_DATA register before the
end of the next reception. Otherwise, reception overrun error occurs. The RXORERR flag is
set and an interrupt may be generated if the ERRIE bit in the SPI_CTL1 register is set. In this
case, it is necessary to disable and then enable I2S before resuming the communication.
For all standards except PCM, the I2SCH flag is used to distinguish the channel side which
the received data belongs to. The I2SCH flag is refreshed at the moment when the RBNE
flag goes high.
Different sequences are used to disable the I2S in different standards, data length and
channel length. The sequences for each case are shown as below Figure 20-53. I2S master
reception disabling sequence.
To Next Page
