GigaDevice Semiconductor GD32F3x0 - Page 347

GD32F3x0 User Manual
347
DMA transfer buffer register (TIMERx_DMATB)
Address offset: 0x4C
Reset value: 0x0000 0000
This register has to be accessed by word (32-bit).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DMATB[15:0]
rw
Bits
Fields
Descriptions
31:16
Reserved
Must be kept at reset value.
15:0
DMATB[15:0]
DMA transfer buffer
When a read or write operation is assigned to this register, the register located at
the address range (Start Addr + Transfer Timer* 4) will be accessed.
The transfer Timer is calculated by hardware, and ranges from 0 to DMATC.
Configuration register (TIMERx_CFG )
Address offset: 0xFC
Reset value: 0x0000 0000
This register has to be accessed by word (32-bit).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
CHVSEL
Reserved
rw
Bits
Fields
Descriptions
31:2
Reserved
Must be kept at reset value.
1
CHVSEL
Write CHxVAL register selection
This bit-field set and reset by software.
1: If write the CHxVAL register, the write value is same as the CHxVAL value, the
write access ignored
0: No effect
0
Reserved
Must be kept at reset value.