GigaDevice Semiconductor GD32F3x0 - Page 346

GD32F3x0 User Manual
346
This register has to be accessed by word (32-bit).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CH3VAL[15:0]
rw
Bits
Fields
Descriptions
31:16
Reserved
Must be kept at reset value.
15:0
CH3VAL[15:0]
Capture or compare value of channel 3
When channel3 is configured in input mode, this bit-filed indicates the counter value
corresponding to the last capture event. And this bit-filed is read-only.
When channel 3 is configured in output mode, this bit-filed contains value to be
compared to the counter. When the corresponding shadow register is enabled, the
shadow register updates every update event.
DMA configuration register (TIMERx_DMACFG)
Address offset: 0x48
Reset value: 0x0000 0000
This register has to be accessed by word (32-bit).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
DMATC[4:0]
Reserved
DMATA [4:0]
rw
rw
Bits
Fields
Descriptions
31:13
Reserved
Must be kept at reset value.
12:8
DMATC [4:0]
DMA transfer count
This filed defines the number(n) of the register that DMA will access(R/W), n =
(DMATC [4:0] +1). DMATC [4:0] is from 5’b0_0000 to 5’b1_0001.
7:5
Reserved
Must be kept at reset value.
4:0
DMATA [4:0]
DMA transfer access start address
This filed define the first address for the DMA access the TIMERx_DMATB. When
access is done through the TIMERx_DMA address first time, this bit-field specifies
the address you just access. And then the second access to the TIMERx_DMATB,
you will access the address of start address + 0x4.