GigaDevice Semiconductor GD32F3x0 - Page 167

GD32F3x0 User Manual
167
0: no effect
1: hold the TIMER5 counter for debugging when the core is halted.
18:17
Reserved
Must be kept at reset value.
16
I2C1_HOLD
I2C1 hold bit
This bit is set and reset by software.
0: no effect
1: hold the I2C1 SMBUS timeout for debugging when the core is halted.
15
I2C0_HOLD
I2C0 hold bit
This bit is set and reset by software.
0: no effect
1: hold the I2C0 SMBUS timeout for debugging when the core is halted.
14:13
Reserved
Must be kept at reset value.
12
TIMER2_HOLD
TIMER2 hold bit
This bit is set and reset by software.
0: no effect
1: hold the TIMER2 counter for debugging when the core is halted.
11
TIMER1_HOLD
TIMER1 hold bit
This bit is set and reset by software.
0: no effect
1: hold the TIMER1 counter for debugging when the core is halted.
10
TIMER0_HOLD
TIMER0 hold bit
This bit is set and reset by software.
0: no effect
1: hold the TIMER0 counter for debugging when the core is halted.
9
WWDGT_HOLD
WWDGT hold bit
This bit is set and reset by software.
0: no effect
1: hold the WWDGT counter clock for debugging when the core is halted.
8
FWDGT_HOLD
FWDGT hold bit
This bit is set and reset by software.
0: no effect
1: hold the FWDGT counter clock for debugging when the core is halted.
7:3
Reserved
Must be kept at reset value.
2
STB_HOLD
Standby mode hold bit
This bit is set and reset by software.
0: no effect
1: In the standby mode, the clock of AHB bus and system clock are provided by
CK_IRC8M, a system reset generated when exiting standby mode.