GigaDevice Semiconductor GD32F3x0 - Register Definition

GD32F3x0 User Manual
563
21.4. Register definition
HDMI-CEC base address: 0x4000 7800
21.4.1. Control register (CEC_CTL)
Address offset: 0x00
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
ENDOM
STAOM
CECEN
rs
rs
rw
Bits
Fields
Descriptions
31:3
Reserved
Must be kept at reset value
2
ENDOM
ENDOM bit value in the next frame in Transmit mode.
ENDOM can only be set by software when CECEN=1. ENDOM is cleared by
hardware in the same situation of clearing STAOM.
0: Next frame send 0 in ENDOM bit position
1: Next frame send 1 in ENDOM bit position
1
STAOM
Start of sending a message.
STAOM can only be set by software when CECEN=1. STAOM is cleared by
hardware if any of these flags asserted: TEND, TU, TAERR, TERR or CECEN is
cleared.
If the message consists of only header frame, ENDOM should be set before
configuring header frame in TDATA. After setting STAOM, the SFT counter will
start and when SFT is done the Start-bit will performance on CEC line. Software
can abort sending the message through clearing CECEN bit under STAOM=1.
0: No CEC transmission is on-going
1: CEC transmission is pending or executing
0
CECEN
Enable/disable HDMI-CEC controller.
CECEN bit is configured by software.
0: Disable HDMI-CEC controller. Abort any sending message state and clear
ENDOM/STAOM
1: Enable CEC controller and go into receiving state if STAOM=0