GigaDevice Semiconductor GD32F3x0 - Page 564

GD32F3x0 User Manual
564
21.4.2. Configuration register (CEC_CFG)
Address offset: 0x04
Reset value: 0x0000 0000
Note: This register can only be write when CECEN=0
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
LMEN
OAD [14:0]
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
SFTOPT
BCNG
BPLEG
BREG
BRES
RTOL
SFT[2:0]
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rw
rw
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Bits
Fields
Descriptions
31
LMEN
Listen Mode Enable Bit
This bit is set and cleared by software.
0: Only receive broadcast and singlecast in OAD address with appropriate ACK
1: Receive broadcast and singlecast in OAD address with appropriate ACK and
receive message whose destination address is not in OAD without feedback ACK
30:16
OAD[14:0]
Own Address
Each bit of OAD represents one destination address. For example: if OAD[0]=1,the
controller will receive the message being sent to address 0x0. This means the
controller can be configured to have multiple own addresses. Broadcast message
is always received.
After received destination address(last 4 bit of HEADER frame),if it is valid in the
OAD, the controller will feedback with positive acknowledge ,if it is not valid in the
OAD and LMEN=1,the controller will receive the message with no acknowledge, if
it is not valid in the OAD and LMEN=0,the controller will not receive the message.
15:9
Reserved
Must be kept at reset value
8
SFTOPT
The SFT start option bit
This bit is set and cleared by software.
0: SFT counter starts counting when STAOM is asserted
1: SFT counter starts automatically after transmission/reception enabled
7
BCNG
Do not generate an Error-bit in broadcast message
This bit is set and cleared by software.
0: In broadcast mode, BRE and BPLE will generate an Error-bit on CEC line and if
LMEN=1, BPSE will also generate an Error-bit
1: Error-bit is not generated in the same condition as above
6
BPLEG
Generate an Error-bit when detected BPLE in singlecast
This bit is set and cleared by software.
0: Not generate an Error-bit on CEC line when detected BPLE in singlecast