GigaDevice Semiconductor GD32F3x0 - Page 565

GD32F3x0 User Manual
565
1: Generate an Error-bit on CEC line when detected BPLE in singlecast
5
BREG
Generate an Error-bit when detected BRE in singlecast
This bit is set and cleared by software.
0: Not generate an Error-bit on CEC line when detected BRE in singlecast
1: Generate an Error-bit on CEC line when detected BRE in singlecast
4
BRES
Whether stop receive message when detected BRE
This bit is set and cleared by software.
0: Do not stop reception for BRE and data bit is sampled at nominal time(1.05ms)
1: Stop reception for BRE
3
RTOL
Reception bit timing tolerance
This bit is set and cleared by software.
0: Standard bit timing tolerance
1: Extended bit timing tolerance
2:0
SFT[2:0]
Signal Free Time
This bit is set and cleared by software.
If SFT=0x0, the SFT time will perform as HDMI-CEC protocol description and if not,
the SFT time is fixed configured by software. The start point is the falling edge of
the ACK bit.
0x0:
- 3x Standard data-bit period if SFT counter is start because of unsuccessful
transmission(ARBF=1,TERR=1,TU=1 or TAERR=1)
- 5x Standard data-bit period if CEC controller is the new initiator
- 7x Standard data-bit period if CEC controller has successful completed
transmission
0x1: 1.5x nominal data bit periods
0x2: 2.5x nominal data bit periods
0x3: 3.5x nominal data bit periods
0x4: 4.5x nominal data bit periods
0x5: 5.5x nominal data bit periods
0x6: 6.5x nominal data bit periods
0x7: 7.5x nominal data bit periods
21.4.3. Transmit data register (CEC_TDATA)
Address offset: 0x08
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0