GD32F3x0 User Manual
512
20. Serial peripheral interface/Inter-IC sound (SPI/I2S)
20.1. Overview
The SPI/I2S module can communicate with external devices using the SPI protocol or the
I2S audio protocol.
The Serial Peripheral Interface (SPI) provides a SPI protocol of data transmission and
reception function in master or slave mode. Both full-duplex and simplex communication
modes are supported, with hardware CRC calculation and checking. Quad-SPI master mode
is also supported in SPI1.
The Inter-IC sound (I2S) supports four audio standards: I2S Phillips standard, MSB justified
standard, LSB justified standard, and PCM standard. I2S works at either master or slave
mode for transmission and reception.
20.2. Characteristics
20.2.1. SPI characteristics
Master or slave operation with full-duplex or half-duplex or simplex mode.
Separate transmission and reception buffer, 16 bits wide.
Data frame size can be 8 or 16 bits.
Bit order can be LSB or MSB.
Software and hardware NSS management.
Hardware CRC calculation, transmission and checking.
Transmission and reception using DMA.
SPI TI mode supported.
SPI NSS pulse mode supported.
Quad-SPI configuration available in master mode (only in SPI1).
20.2.2. I2S characteristics
Master or slave operation for transmission/reception.
Four I2S standards supported: Phillips, MSB justified, LSB justified and PCM standard.
Data length can be 16 bits, 24 bits or 32 bits.
Channel length can be 16 bits or 32 bits.
Transmission and reception using a 16 bits wide buffer.
Audio sample frequency can be 8 kHz to 192 kHz using I2S clock divider.
Programmable idle state clock polarity.
Master clock (MCK) can be output.
Transmission and reception using DMA.
To Next Page
