GigaDevice Semiconductor GD32F3x0 - Register Definition

GD32F3x0 User Manual
543
20.5. Register definition
SPI0/I2S0 base address: 0x4001 3000
SPI1 base address: 0x4000 3800
20.5.1. Control register 0 (SPI_CTL0)
Address offset: 0x00
Reset value: 0x0000 0000
This register can be accessed by byte (8-bit) or half-word (16-bit) or word (32-bit).
This register has no meaning in I2S mode.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BDEN
BDOEN
CRCEN
CRCNT
FF16
RO
SWNSS
EN
SWNSS
LF
SPIEN
PSC [2:0]
MSTMOD
CKPL
CKPH
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits
Fields
Descriptions
31:16
Reserved
Must be kept at reset value.
15
BDEN
Bidirectional enable
0: 2 line unidirectional transmit mode
1: 1 line bidirectional transmit mode. The data transfers between the MOSI pin of
master and the MISO pin of slave.
14
BDOEN
Bidirectional transmit output enable
When BDEN is set, this bit determines the direction of transfer.
0: Work in receive-only mode
1: Work in transmit-only mode
13
CRCEN
CRC calculation enable
0: Disable CRC calculation.
1: Enable CRC calculation.
12
CRCNT
CRC next transfer
0: Next transfer is data
1: Next transfer is CRC value
When the transfer is managed by DMA, CRC value is transferred by hardware.
This bit should be cleared.
In full-duplex or transmit-only mode, set this bit after the last data is written to
SPI_DATA register. In receive only mode, set this bit after the second last data is