GOWIN GW2A-55 User Manual (English)

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Gowin FPGA Products

Programming and Configuration Guide

UG290-2.3E, 02/07/2021

Table of Contents4
List of Figures6
About this Guide10
Purpose10
Related Documents10
Terminology and Abbreviations10
Table 1-1 Abbreviations and Terminology10
Support and Feedback11
Glossary12
Table 2-1 Glossary12
Configuration Modes14
Littlebee ® Family of FPGA Products14
Arora Family of FPGA Products15
Table 3-1 Configuration Modes15
Table 3-2 Configuration Modes16
Configuration Pin17
Configuration Pin List and Reuse Options17
Configuration Pin List17
Table 4-1 Configuration Pin List17
Configuration Pin Multiplexing18
Table 4-2 Pin Reuse Options19
Configuration Pin Function and Application20
Figure 4-1 Configuring Pin Reuse20
Table 4-3 Pin Function20
Figure 4-2 MCLK Frequency Setting23
Configuration Mode Introduction25
Configuration Notes25
Figure 5-1 Recommended Pin Connection27
Figure 5-2 Power Recycle Timing27
JTAG Configuration28
Figure 5-3 Trigger Timing28
Table 5-1 Timing Parameters for Cycling Power and RECONFIG_N Trigger28
Table 5-2 Timing Parameters for Power-On Again and RECONFIG_N Triggering (Arora Family)28
JTAG Configuration Mode Pins29
Table 5-3 Pin Description in JTAG Configuration Mode29
Connection Diagram for the JTAG Configuration Mode30
Figure 5-4 Connection Diagram for JTAG Configuration Mode30
JTAG Configuration Timing31
Figure 5-5 Connection Diagram of JTAG Daisy-Chain Configuration Mode31
Figure 5-6 JTAG Configuration Timing31
Table 5-4 JTAG Configuration Timing Parameters31
JTAG Configuration Process32
Figure 5-7 TAP State Machine32
Figure 5-8 Instruction Register Access Timing33
Figure 5-9 Data Register Access Timing33
Table 5-5 Gowin FPGA IDCODE34
Table 5-6 Change of TDI and TMS Value in the Process of Sending Instructions34
Figure 5-10 Read Machine Flow Chart in ID Code State35
Figure 5-11 the Access Timing of Read ID Code Instruction- 0X1135
Figure 5-12 Read ID Code Data Register Access Timing36
Figure 5-13 SRAM Configuration Flow37
Table 5-7 Count of Address and Length of One Address38
Figure 5-14 Process of Reading SRAM39
Table 5-8 TCK Frequency Requirements for JTAG40
Figure 5-15 the Embedded Flash Erasing Process of T Technology41
Figure 5-16 the Embedded Flash Erasing Process of S Technology43
Table 5-9 Readback-Pattern / Autoboot-Pattern44
Figure 5-17 Process of Programming Internal Flash View45
Figure 5-18 X-Page Programming46
Figure 5-19 Y-Page Programming47
Figure 5-20 Process of Reading Internal Flash48
Figure 5-21 Process of Reading a Y-Page49
Figure 5-22 GW1N-4 Background Programming Flow50
Figure 5-23 Transfer JTAG Instruction Sample & Extest Flow Chart51
Figure 5-24 Connection Diagram of JTAG Programming External Flash52
Figure 5-25 Process View of Programming SPI Flash SPI52
Figure 5-26 Timing Diagram of Sending 0X06 Via GW2A Series JTAG Simulating SPI53
Figure 5-27 Timing Diagram of Sending 0X06 Via GW1N Series JTAG Simulating SPI53
Table 5-10 Pin State53
Figure 5-28 Process of Use Boundary Scan Mode to Program SPI Flash54
Table 5-11 Status Register Definition55
AUTO BOOT Configuration (Supported by Littlebee Family Only)56
Figure 5-29 Connection Diagram of Daisy-Chain56
Sspi58
SSPI Mode Pins58
Table 5-12 SSPI Mode Pins58
SSPI Configuration Timing59
Configuration Instruction59
Figure 5-30 SSPI Configuration Timing59
Table 5-13 SSPI Configuration Timing Parameters59
Figure 5-31 Read ID Code Timing60
Table 5-14 Configuration Instruction60
Figure 5-32 Write Enable (0X15) Timing61
Figure 5-33 Write Disable(0X3A00) Timing61
Figure 5-34 Write Data (0X3B) Timing62
Connection Diagram for SSPI Configuration Mode63
Figure 5-35 SSPI Configuration Mode Connection Diagram63
Figure 5-36 Connection Diagram of Programming External Flash Via SSPI63
Figure 5-37 the Flow of Programming External Flash Via SSPI64
Multiple FPGA Connection View in SSPI Mode65
Mspi65
Figure 5-38 Multiple FPGA Connection Diagram 165
Figure 5-39 Multiple FPGA Connection Diagram 265
Table 5-15 Pin Description in JTAG Configuration Mode66
Figure 5-40 Connection Diagram for MSPI Configuration Mode67
Figure 5-41 Connection Diagram of JTAG Programming External Flash67
Figure 5-42 Input the Start Address for the Next Bitstream68
Figure 5-43 Set the Programming Address for the External Flash69
Figure 5-44 Connection Diagram for Configuring Multiple Fpgas Via Single Flash70
Figure 5-45 MSPI Download Timing70
DUAL BOOT Configuration (Supported by Littlebee Family Only)71
Figure 5-46 Multiple FPGA Connection Diagram in MSPI Configuration Mode71
Table 5-16 MSPI Configuration Timing Parameters71
Figure 5-47 Dual Boot Flow Chart72
CPU Mode73
Table 5-17 CPU Mode Pins73
Configuration Timing74
SERIAL Mode74
Figure 5-48 Connection Diagram for CPU Mode74
Figure5-49 CPU Mode Configuration Timing74
Figure 5-50 Connection Diagram for SERIAL Mode75
Figure 5-51 SERIAL Configuration Timing75
Table 5-18 Pin Definition in SERIAL Configuration Mode75
I 2 C Mode76
Table 5-19 SERIAL Configuration Timing Parameters76
Table 5-20 Pin Definition in SERIAL Configuration Mode76
Figure 5-52 Connection Diagram for I 2 C Mode77
Figure 5-53 I 2 C Mode Timing77
Table 5-21 I 2 C Configuration Timing Parameters77
Bitstream File Configuration79
Configuration Options79
Configuration Data Encryption (Supported by Arora Family Only)80
Definition80
Figure 6-1 Configuration Options80
Enter Encryption KEY81
Enter the Decrypt Key81
Figure 6-2 Encryption Key Setting Method81
Programming Operation82
Figure 6-3 Setting the Decryption Key82
Figure 6-4 AES Security Configure83
Programming Flow84
Figure 6-5 Prepare84
Figure6-6 Read AES Key Flow85
Figure 6-7 Program AES Key Flow86
Configuration File Size87
Figure 6-8 Lock AES Key Flow87
Configuration File Loading Time88
Figure 6-9 Bitstream Format Generation88
Table 6-1 Gowin FPGA Products Configuration File Size (Max.)88
Table 6-2 Loading Frequency of Config File89
Table 6-3 Loading Time in MSPI Mode91
Table 6-4 Loading Time in Autoboot Mode91
Safety Precautions92
Boundary Scan94
Figure 8-1 Boundary Scan Operation Schematic Diagram95
SPI Flash Selection96

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GOWIN GW2A-55 Specifications

General

Family	Arora
Logic Cells/Elements	55K
Max I/O Pins/User I/O	400
DSP Blocks	144
Process Technology	55 nm
Operating Voltage	1.2V
Package Type	QFN, BGA
Category	FPGA
Operating Temperature	-40°C to 100°C
Arora Family	Arora

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