Grundig Vision 4 32-4805 T - Übersicht

GRUNDIG Service Chassis BL (LX prime IDTV)
2 - 43
Übersicht / Overview
MADR[0..11]
RXE0-/GA3
RXE0+/GA2
RXE1-/GA1
RXE1+/GA0
RXE2-/BA7
RXE2+/BA6
RXEC-/BA5
RXEC+/BA4
RXE3-/BA3
RXE3+/BA2
VPANEL
RXO0-/RA7
RXO0+/RA6
RXO1-/RA5
RXO1+/RA4
RXO2-/RA3
RXO2+/RA2
RXOC-/RA1
RXOC+/RA0
RXO3-/GA7
RXO3+/GA6
Scaler P. 2-34
ON_PBACK
ON_PANEL
ST.BY
ST.BY
24VSENSE
24VSENSE
VPANEL
Power P. 2-25
GIN+
GIN-
BIN+
BIN-
VS_RGB
HS_RGB
SOG
RIN+
RIN-
TXD
RXD
AU_SWA
AUR0
AUL0
COMPR
SPDIF
VGA Socket P. 2-27
I2C_SCL
I2C_SDA
SIFP0
SIFM0
AUMONO
TUN_CVBS
VCOM0
ANTPOWER
TS_DATA[0..7]
TS_CLK
TS_VALID
TS_START
RESET_COFDM
SDA_COFDM
SCL_COFDM
Tuner / COFDM Demodulator P. 2-31
MUTE_S
LOUD_OUT_R
LOUD_OUT_L
HP_OUT_R
HP_OUT_L
ST.BY
AUOut_R1
AUOut_L1
+3.3V
Amplifier P. 2-33
MDATA[0..15]
ON_PBACK
ON_PANEL
PWM0
PWM0
BR_IN
BR_OUT
BR_IN
BR_OUT
GIN+
GIN-
BIN+
BIN-
VS_RGB
HS_RGB
SOG
RIN+
RIN-
AUR0
AUL0
COMPL
TXCLK-
TXCLK+
TX0-
TX0-+
TX1-
TX1+
TX2-
TX2+
HPDCTRL
I2C_SCL
I2C_SDA
HDMI_INT
HDMI Sockets P. 2-28
TXCLK-
TXCLK+
TX0-
TX0-+
TX1-
TX1+
TX2-
TX2+
HPDCTRL
#RESET
RESET
#RESET
SCL_HD
SDA_HD
SIFP0
SIFM0
PIP_Y
PIP_C
PIP_CVBS
DCR_ON
RTC_INT
RX_Scart 2
TX_Scart 2
TUNER_CVBS
DELAY
A/D
SCL5V
SDA5V
SC1_CVBS
SC1_OUT
TUN_CVBS
SC1_FSW
AUL1
AUR1
AUOutL3
AUOutR3
SCG+
SCR+
SCB+
SC_CVBS1
SCG-
SCB-
SCR-
AUOutL2
AUOutR2
SC1_Mode
VCOM1
SC2_CVBS
PIP_CVBS
SCART Sockets P. 2-30
AUWS
AUSD0
AUSCK
AUMCK
DVB_CVBS
SVHS_Y
SVHS_C
FAV_CVBS
I2C_SCL
SC2_OUT
AUL3
AUR3
AUOutL2
AUOutR2
SC1_FSW
SCG+
SCR+
SCB+
SC_CVBS1
SCG-
SCB-
SCR-
SC2_Mode
TXD
RXD
I2C_SCL
I2C_SDA
SC2_Mode
SC2_Chroma
SC_Chroma
SC_CVBS2
SC_CVBS1
DVB_CVBS
SC_Chroma
SC_CVBS2
PIP_Y
PIP_C
AUWS
AUSD0
AUSCK
AUMCK
SV_Y0
SV_C0
SPDIF_OUT
SVHS_Y
SVHS_C
VCOM2
FAV_L
FAV_R
FAV_CVBS
VCOM1
AUL2
AUR2
CVBS1
SOY
Y+
PB+
PR+
Y-
PB-
PR-
AV Sockets P. 2-29
SPDIF_OUT
SV_Y0
SV_C0
VCOM2
VCOM1
AUL1
AUR1
AUL2
AUR2
CVBS1
SPDIF
MUTE_S
ST.BY
AUOut_R
AUOut_L
+3.3V
+5V_SW
+12V
+24V
KEY_IN_Z-Touch (KEY_IN)
IR_Z-Touch (IR_IN)
SDA_Z-Touch (SDA2)
SCL_Z-Touch (SCL2)
+5V
+3.3V
+2.5V
+1.8V
+1.2V
+5V_SW
+9V
+9V_A
+5V
+9V_A_SCART2
+9V_A_SCART1
+9V_A
+9V
+5V_SW
+5V
+5V
+3.3V
+1.8V
+12V
+12V_SW
+24V
+33V
AVDD_DVI (3.3V)
AVDDA (3.3V)
AVDD_SIF (3.3V)
AVDD_AU (3.3V)
AVDD_MemPLL (3.3V)
AVDD_MPLL (3.3V)
VDDP (3.3V)
VDDC (1.2V)
VDDM (2.5V)
+24V_PANEL
+3.3V
+DMQ (+2.5V)
+DMC (+2.5V)
+2.5V
+1.8V
+5V
+5V_SW
+12V
AVDD_DVI (3.3V)
AVDDA (3.3V)
AVDD_SIF (3.3V)
AVDD_AU (3.3V)
AVDD_MemPLL (3.3V)
AVDD_MPLL (3.3V)
VDDP (3.3V)
VDDC (1.2V)
VDDM (2.5V)
I2C_SDA
+3V3A_DIG_FE
+3.3V
+1V2D_DIG_FE
+1V2A_DIG_FE
+1.2V
+3V3D_DIG_FE
+5V
+5V-IF
+5V_OUT
+5V_SW
SCL_HD
SDA_HD
SOY
Y+
PB+
PR+
Y-
PB-
PR-
VCOM0
TUNER_CVBS
TS_DATA[0..7]
TS_CLK
TS_VALID
TS_START
ANTPOWER
RESET_COFDM
SDA_COFDM
SCL_COFDM
ITU…
Power Supply
IDTV Board
ID_TS_ERROR
TS_CLK
TS_VALID
TS_SYNC
TS_DATA[0..7]
RDATA[0..15]
RADDRESS[0..22]
CI_DIR
RXD1B
TXD1B
TXD1B
RXD1B
TS_SW
EMI_SW
656CLK
656…
SCL_MD
SDA_MD
CI_CD2
CI_REG
CI_INPACK
CI_RESET
CI_IOWR
CI_IORD
CI_IREQ
CI_CD1
CI_VS1
MPEG_ABCK
MPEG_AMCK
MPEG_ADO
MPEG_SPDIF
GRDYB
MPEG_ALRCK
FWEB
FOEB
GCS0B
FCSB0
D_CVBS_IN
RADDRESS22
RESET
F_RESET
RXD0B
TXD0B
ANT_POW
MPEG Decoder & CPU
F_RESET
RADDRESS22
TS_TUN_DATA[0..7]
TS_SW
TS_TUN_CLK
TS_TUN_SYNC
TS_TUN_VALID
TS_DATA[0..7]
FCSB0
CI_DIR
EMI_SW
RDATA[0..15]
TS_CLK
TS_SYNC
TS_VALID
CI_IREQ
CI_CD1
CI_VS1
CI_CD2
CI_REG
CI_INPACK
CI_RESET
CI_IOWR
CI_IORD
GRDYB
FWEB
FOEB
GCS0B
RADDRESS[0..22]
Common InterfaceP. 2-40 P. 2-40 P. 2-42
RX_Scart 2
TX_Scart 2
ST.BY
+5V
+5V_SW
TS_DATA[0..7]
TS_CLK
TS_VALID
TS_START
ITU656D[0..7]
ANTPOWER
RESET_COFDM
SDA_COFDM
SCL_COFDM
RX_DVB
TX_DVB
RESET_DVB
AISCK
AIWS
DVB_CVBS
SPDIF_IN
AISD
RXD1B
TXD1B
RESET_DVB
MPEG_ABCK
MPEG_ALRCK
D_CVBS_IN
MPEG_SPDIF
MPEG_ADO
ST.BY
ST.BY
+5V_DVB
3V3_ASTBY
+5V_DVB
3V3_ASTBY
2V5_ASTBY
1V5_ASTBY
TS_TUN_DATA[0..7]
TS_TUN_CLK
TS_TUN_VALID
TS_TUN_SYNC
656D[0..7]
ANT_POW
F_RESET
SDA_MD
SCL_MD
ITU_CLK 656CLK