HP 3457A - 8-76. Power-on Self Test; 8-77. Self Test (TEST)

8-76. Power-on Self Test
At instrument power-on, an abbreviated form of the complete Self Test procedure is executed to check
the fundamental digital hardware kernel and the communication link between the Main Controller
(A1USO01) and A/D Controller (A2U501). This consists of executing Self Tests 0, 1 and 2 in that order.
These 3 tests are discussed in detail in the following Self Test paragraphs.
Upon satisfactory completion of the power-on test routine, the instrument momentarily displays the
HP-IB address it is currently set to (the address is set to decimal 22 at the factory), emits a single "beep"
and sets itself to the predefined power-on state. The front panel indications of this state are; the DC
Voltage function, Auto-Range and automatic trigger are selected. For a complete list of power-on con-
ditions, refer to Section III, Table 3-1 in this manual.
8-77. Self Test (TEST)
In addition to the 3 Power-on Self Tests, 7 other self tests may be executed by using the TEST com-
mand, All self tests are executed sequentially when the TEST command is executed and cannot be ex-
ecuted individually; however, the self tests are separated and numbered below to aid in troubleshooting.
Test 0 checks much of the circuitry on the Main Controller assembly Al. There are 5 subtests included
in Test 0 and they are executed in the following sequence: 1) U502 ROM Checksum, 2) U503 ROM
Checksum, 3) Nonvolatile RAM (USI1), 4) Volatile RAM (U506), and 5) Calibration RAM (US5I1)
and
RAM
write
protection
circuitry.
These
are
also
checked
as
part
of
the
power-on
test.
The ROM checksum tests against hard coded results. If the checksum of U502 is incorrect, executing
the AUXERR? command will return a value of 1024. If the checksum of U503 is incorrect, executing
the AUXERR? command will return a value of 2048. During the nonvolatile RAM test, FF, 55, 00 is
written to each RAM location and read back (data presently in RAM is preserved). If the nonvolatile
RAM test fails, the AUNERR? command would return 4096. The test on the volatile RAM is the same
as the test on the nonvolatile RAM; however, the AUXERR? command would return 8192. The last
part of test 0 writes to the protected portion of the nonvolatile RAM and reads back. If the informa-
tion written is read back, this indicates the RAM is not protected. In this case the AUXERR? command
would return the value 16384.
Test 1 checks the A/D Controller (A2U501) reset procedure. RAM and ROM. Reset occurs primarily
at power-on; however, Main Controller (A1U501) can force an A/D Controller hard reset by sending
continuous 0 bytes across the communications link (A2U509/U510) for greater than 10mS. While
checking the A/D Controller RAM and ROM, the A/D Controller performs the tests described below
while
the
Main
Controller
(A1U501)
checks
the
reported
results
against
hard
coded
limits.
1. The A/D Controller RAM Test writes 55, 00 to each RAM location and reads it back. A RAM test
failure will force the reported ROM checksum result to be in error. On failure, the AUXERR? com-
mand will return the value 2.
2. The A/D Controller ROM Test performs a checksum on the ROM and transmits the results to Main
Controller A1U501. On failure, the AUXERR? command will return the value 2.
A subset of self test 1 is diagnostic | which will cause the A/D Controller to continually loop through
the Test | routine. Executing DIAGNOSTIC I allows monitoring of signals while troubleshooting.
Test 2 is a cross-isolation data communications test that transmits data between the Main Controller
(A1USOL) and the A/D Controller (A2U501) through opto-isolators A2U509/U510. The Main
Controller will transmit a sequence of codes to the A/D Controller which will "ECHO BACK" these
transmissions, as it receives them, to the Main Controller. The data returned to the Main Controller is
HP 3457A Multimeter
8-38