HP 3457A - Page 205

~Vref
U511
A/D
HYBRID
DSA_TEST STIMULUS
COMPARE IN
ANALOG AUTO ZERO
34520 F.12.22
Figure 8-5. Integrator Convergence Circuitry
Test 4 is the front-end zero offset test on assembly A2/1. This test measures the input amplifier (QII1,
QI12, ULL) input offset voltage and sends the result to the Main Controller (A1U501) for error chech-
ing. This test does not require any previous instrument calibration.
The Main Controller configures the isolated section (A2U5O01) for 0.03 volts DC with 1.0 power line
cycle of integration time. An offset measurement is made on the 30mV range (gain = 333) through
A2U101 switch MC followed by a measurement on the 3V range (gain 33) through switch MC. This
yields a result that is the input offset multiplied by 330. This result is scaled for the 30mV range using
the latest cal constants. The Main Controller checks that the result is within the limits of 0 41.5m¥
Figure 8-6 illustrates some of the circuitry used for this test.
On error, if the AUXERR? command is executed, the number 16 will be displayed on the control panel
if their are no other errors (See Table 8-2). If this error occurs, an mechanical adjustment may
correct the error. To perform the adjustment, execute DIAGNOSTIC 4 and adjust the input amplifier
offset adjustment (A2R113). Refer to the Input Amplifier Offset Procedure in section 5 for details. If
adjustment does not correct the error, DIAGNOSTIC 4 can also be used for troubleshooting because it
puts this test into a looping condition so signals may be verified.
HP 3457A Multimeter
8-40