Huawei MU509 - JTAG Interface Design Guide

HUAWEI 30 mm × 30 mm LGA Module
Hardware Migration Guide
LGA Interface Differences
Issue 08 (2016-12-12)
HUAWEI Proprietary and Confidential
Copyright © HUAWEI Technologies Co., Ltd.
40
Pin
No.
Interface
Name
MC509
MU509
MU609
ME209u-
526
ME909u
MU709
ME909s
72
JTAG_TDO
87
JTAG_TDI
93
JTAG_RTC
K
CMOS 1.8 V
Reserved
CMOS
1.8 V
14
PS_HOLD
CMOS 1.8 V
CMOS 1.8 V
N
100/
47
RESIN_N/JT
AG_SRST_
N
CMOS 1.8 V (pin 100)
JTAG_SRST_N
(pin 47) reset for
JTAG debugging
CMOS
1.8 V (pin
100)
RESIN_
N (pin
100)
2.8.2 JTAG Interface Design Guide
To facilitate fault location, it is recommended that you lead out JTAG signals from test
points. The LGA module must be reserved with JTAG test point interfaces for fault
analysis and location. The JTAG interface signals include the following signals.
Arrange test points according to the following relationship.
The following figure shows the connections of JTAG signal pins.