Huawei MU509 - UART Interface Design Guide

HUAWEI 30 mm × 30 mm LGA Module
Hardware Migration Guide
LGA Interface Differences
Issue 08 (2016-12-12)
HUAWEI Proprietary and Confidential
Copyright © HUAWEI Technologies Co., Ltd.
42
Table 2-16 Differences of the UART interface
Pin
No.
Interface
Name
MU509
MC509
MU609
MU709
ME209u-526
ME909u
ME909s
73
UART
UART0_DSR
CMOS 2.6 V
CMOS 1.8 V
N
CMOS 1.8
V
74
UART0_RTS
CMOS 2.6 V
CMOS 1.8 V
75
UART0_DCD
CMOS 2.6 V
CMOS 1.8 V
N
CMOS 1.8
V
76
UART0_TX
CMOS 2.6 V
CMOS 1.8 V
77
UART0_RIN
G
CMOS 2.6 V
CMOS 1.8 V
N
CMOS 1.8
V
78
UART0_RX
CMOS 2.6 V
CMOS 1.8 V
CMOS 1.8
V
79
UART0_DTR
CMOS 2.6 V
CMOS 1.8 V
N
CMOS 1.8
V
80
UART0_CTS
CMOS 2.6 V
CMOS 1.8 V
CMOS 1.8
V
1
UART1_TX
N
N
CMOS 1.8 V for
debugging
CMOS 1.8 V
N
2
UART1_RTS
N
N
N
N
CMOS 1.8 V
N
3
UART1_CTS
N
N
N
N
CMOS 1.8 V
N
4
UART1_RX
N
N
CMOS 1.8 V for
debugging
CMOS 1.8 V
N
28
UART2_TX
Reserved
CMOS 1.8 V for debugging
29
UART2_RX
Reserved
CMOS 1.8 V for debugging
2.9.2 UART Interface Design Guide
Besides compatibility of the UART, designers must consider the time sequence of
signals. The UART signals externally connected with the LGA module must be
transmitted at least 3s after the LGA module is powered on. Otherwise, a sink current
occurs and the LGA module may be improperly powered on.