ICP Electronics JUKI- 745E - Table of Contents

1
Table of Contents
CHAPTER 1. INTRODUCTION............................................ 2
1.1 S
PECIFICATIONS ...........................................................3
1.2 P
ACKAGE CONTENTS ......................................................5
CHAPTER 2. INSTALLATION ............................................. 6
2.1 JUKI-745E L
AYOUT .....................................................6
2.2 S
ETTING THE CPU OF JUKI-745E .....................................8
2.3 D
ISKONCHIP™ FLASH DISK .......................................... 10
2.4 LCD V
OLTAGE SETTING ................................................ 10
2.5 C
LEAR CMOS SETUP ................................................... 11
2.6 B
ATTERY BACKUP FOR CMOS SETUP ................................. 11
2.7 BIOS F
LASH CHIP WRITE VOLTAGE SETTING ....................... 11
CHAPTER 3. CONNECTION.............................................. 12
3.1 F
LOPPY DISK DRIVE CONNECTOR...................................... 12
3.2 PCI E-IDE D
ISK DRIVE CONNECTOR ................................ 13
3.3 P
ARALLEL PORT .......................................................... 14
3.4 S
ERIAL PORTS ........................................................... 15
3.5 K
EYBOARD / MOUSE CONNECTOR ..................................... 16
3.6 E
XTERNAL SWITCHES AND INDICATORS............................... 17
3.7 E
XTERNAL BATTERY CONNECTOR ...................................... 18
3.8 LCD/CRT C
ONNECTOR................................................. 18
3.9 L
AN RJ45 CONNECTOR ................................................. 19
3.10 USB P
ORT ............................................................... 20
3.11 IO A
DDRESS MAP ....................................................... 20
CHAPTER 4. AMI BIOS SETUP ....................................... 23
4.1 G
ETTING START.......................................................... 23
4.2 S
TANDARD CMOS SETUP .............................................. 24
4.3 A
DVANCED CMOS SETUP .............................................. 24
4.4 A
DVANCED CHIPSET SETUP............................................. 24