Integra DHC-9.9

IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS-61
Q8501 : SII9135ACTU (HDMI Receiver)
BLOCK DIAGRAM
TX-SR876/SA876
MCLK
Gen
I C
Slave
2
Registers
Configuration
Logic Block
I C
Slave
2
XOR
Mask
DSDA0
Aux
Data
HDMI
Mode
Control
Auto A/V
Exception
Handling
Port
Detect
HDCP
Embedded
Keys
HDCP &
Repeater
Decryption
Engine
Port
MUX
TMDS
Digital
Core
TMDS
Digital
Core
Port
MUX
Audio
Data
Decode
Video
Deep Color
Color Space
Converter
Up/Down
Sampling
36
24-Bit
Data
HS, VS,
DE
HS, VS,
DE
36-Bit
Data
24/30/36-Bit
Encrypted Pixel
Data
24/30/36-Bit
Decrypted Pixel
Data
Control Signals
INT
CSDA
CSCL
RESET#
DE
SPDIF
MCLKOUT
SCK
WS
DCLK
XTALIN
XTALOUT
HSYNC
VSYNC
ODCK
Q[35:0]
SD[3:0]
DL[3:0]
DR[3:0]
EVNODD
MUTEOUT
SCDT
DSCL0
DSDA1
DSCL1
R0XC
R0X0
R0X1
R0X2
R0PWR5V
R1PWR5V
R1XC
R1X0
R1X1
R1X2
w w w . x i a o y u 1 6 3 . c o m
Q Q
3
7
6 3
1 5 1 5
0 9 9
2
8 9
4 2
9 8
T E L 1 3 9 4 2 2 9 6 5 1 3 9 9 2 8 9 4 2 9 8 0 5 1 5 1 3 6 7 3
Q Q
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