Integra DHC-9.9

Q1002: IS25C32A(32 kbit EEPROM)
BLOCK DIAGRAM
TERMINAL DESCRIPTION
IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -82
DTR-8.9
PIN CONFIGURATION
STATUS
REGISTER
4096 x 8
MEMORY ARRAY
HOLD
CS
WP
CLOCK
SO
OUTPUT
BUFFER
SCK
SI
DATA
REGISTER
MODE
DECODE
LOGIC
GND
VCC
ADDRESS
DECODER
1
2
3
4
8
7
6
5
CS
SO
WP
GND
VCC
HOLD
SCK
SI
CS Chip Select
SCK Serial Data Clock
SI Serial Data Input
SO Serial Data Output
GND Ground
V
CC Power
WP Write Protect
HOLD Suspends Serial Input
w w w . x i a o y u 1 6 3 . c o m
Q Q
3
7
6 3
1 5 1 5
0 9 9
2
8 9
4 2
9 8
T E L 1 3 9 4 2 2 9 6 5 1 3 9 9 2 8 9 4 2 9 8 0 5 1 5 1 3 6 7 3
Q Q
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