MEMORY MANAGEMENT AND VIRTUAL ADDRESSING
automatically loads the hidden "descriptor" portion of LDTR with five bytes from the chosen LDT
descriptor. Thus, size and base information about a particular LDT,
as
recorded in a memory-resident
global descriptor table entry,
is
cached in the LDTR register.
New values may
be
loaded into the visible portion of the LDTR (and, thus, into the hidden portion
as
well) in either of two ways. The LLDT instruction, during system initialization,
is
used explicitly to set
an initial value for the
LDTR
register; in this way, a local address space
is
provided for the first task
in a multitasking environment. After system startup, explicit changes are not required since operations
that automatically invoke a task switch (described in section 8.4) appropriately manage the LDTR.
At all times, the
LDTR
register thus records the physical base address (and size) of the current task's
LDT; the descriptor table required for mapping the current local address space, therefore,
is
immedi-
ately accessible to the processor. Moreover, since GDTR always maintains the base address of the
GDT, the table that maps the global address space
is
similarly accessible. The two system address
registers,
GDTR
and LDTR, act
as
a special processor cache, maintaining current information about
the two descriptor tables required, at any given time, for addressing the entire current virtual address
space.
6-13
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