PROGRAMMING NUMERIC APPLICATIONS
the operand
in
memory. In table
2-14,
the first figure gives execution clocks for even-addressed operands,
while the second gives the clock count for odd-addressed operands.
For operands aligned at
word boundaries, that
is,
based
at
even memory addresses, each word to be
transferred requires one bus cycle between the 80286 data channel and memory, and one bus cycle to
the NPX. For operands based
at
odd
memory addresses, each' word transfer requires
two
bus cycles to
transfer individual bytes ,between the 80286 data channel and memory, and one bus cycle
to
the NPX.
NOTE
For best performance, operands for the 80287 should be aligned along word boundaries; that
is, based at even memory addresses. Operands based at odd memory addresses are transferred
to memory
essentially- byte-at-a-time and may take half again as long to transfer as word-
aligned operands.
Additional transfer time
is
required
if
slow memories are being used, requiring the insertion of wait
states into the
CPU
bus cycle.
In
multiprocessor environments, the bus may not be available immedi-
ately; this overhead can also increase effective transfer time.
INSTRUCTION LENGTH
80287 instructions that do not reference memory are two bytes long. Memory reference instructions
vary between two and four bytes. The third and fourth bytes are for the
8-
or 16-bit displacement
values used in conjunction with the standard 80286 memory-addressing modes.
Note
that the lengths quoted in table 2-14 for the processor control instructions (FNINIT, FNSTCW,
FNSTSW, FNSTSW AX, FNCLEX, FNSTENV, and
FNSA
VE) do not include the one-byte
CPU
wait instruction inserted by the ASM286 assembler if the control instruction
is
coded using the wait
form of the mnemonic (e.g.
FINIT,
FSTCW, FSTSW, FSTSW AX, FCLEX, FSTENV, and FSAVE).
wait and no-wait forms of the processor control instructions have been described in the preceding section
titled "Processor Control Instructions."
2-23
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