SYSTEM CONTROL AND INITIALIZATION
SLDT (store LDT) can be executed
at
any privilege level. SLDT stores the local descriptor table
selector from the program visible portion of the LDTR register.
Task Register loading or storing
is
again similar to that of the LDT. The LTR instruction, operating
only at level
0,
loads the L
TR
at initialization time with a selector
for
the initial TSS. L
TR
does
NOT
cause a task switch; it just changes the current Note that the busy bit of the old TSS descriptor
is
not changed while the busy bit of the
new
TSS selector must
be
zero and
will
be
set by LTR. The
LDT and any segment registers referring
to
the old LDT should
be
reloaded. STR, which permits the
storing of
TR
contents into memory, can
be
executed at any privilege level. LTR
is
not usually needed
after initialization because the
TR
is
managed
by
the task-switch operation.
10.2.2 Machine Status Word
The Machine Status Word (MSW) indicates the 80286 configuration and status.
It
is
not part of a
task's state. The MSW word
is
loaded
by
the LMSW instruction executed in real address mode or at
privilege level 0 only, or
is
stored by the SMSWinstruction executing at any privilege level. MSW
is
a 16-bit register, the lower four bits of which are used
by
the 80286. These bits have the meanings
shown in table
10-1. Bits 15-4 of the MSW will
be
used by the 80386. 80286 software should not
change these bits.
If
the bits are changed by the 286 software, compatibility with the 80386
will
be
destroyed.
The TS flag
is
set under hardware control and reset under software control. Once the TS flag
is
set,
the next instruction using a processor extension causes a processor extension not-present exception (#7).
This feature allows software
to
test whether the current processor extension state belongs
to
the current
task
as
discussed
in
section 11.4.
If
the current processor extension state belongs
to
a different task,
the software can save the state of any processor extension with the state of the task that uses it. Thus,
the TS bit protects a task from.processor extension errors that result from the actions of a previous
task. .
The CL TS instruction
is
used
to
reset the TS flag after the exception handler has set up the proper
processor extension state. The CLTS instruction can be executed at privilege level 0 only.
Table 10-1. MSW Bit Functions
Bit
Name Function
Position
0
PE Erotected mode
e.nable
places the 80286 into protected mode and cannot be
cleared except by
RESET.
i
ivit'
Munitor'
jJfOCt;55UI eXLeiiSioii
to
a
nrn,..OQc::nr
....
------
. .
extension not-present exception (number
7)
if TS is also set.
2
EM
Emulate processor extension causes a processor extension not-present excep-
tion (number
7)
on
ESC instructions to allow a processor extension to be emulated.
3
TS
Iask
switched indicates the next instruction using a processor extension will cause
exception
7,
allowing software to test whether the current processor extension
context belongs to the current task.
10-4
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