Intel 80286 User Manual

80286 BASE ARCHITECTURE
STACK OPERATION FOR CODE SEQUENCE: STACK
SEGMENT
PUSH AX
POP AX
POPBX 1062 0 0 0
0
1060
lOSE
2 2 2
2
105C
3
3 3 3
OF STACK
105A 4
4 4 4
1058 5
5 5 5
I
1056
6 6
6 6
I
SS
SP
1054
7 7
7
I
SELECTOR I
I
NOT PRESENTL V
OFFSET
1052
8 8 8
8
USED
I
1050 9 9
9
9
00001
I
EXISTING STACK BEFORE PUSH
STACK
SEGMENT
1062 0 0
0
0
1060
1
lOSE 2 2 2
105C
3 3 3 3
105A 4
4 4 4
1058 5 5
5 5
PUSH AX
1056 A
A A
A-4
A A A A
I
SS
SP
1054
I SELECTOR I
I
1052 8 8 8 8
OFFSET
1050 9 9
9 9
00001
I
STACK
SEGMENT
1062 0 0
0
0
1060
lOSE
2 2
2
POP BX
105C
3
3 3
:3
15
5
5 5
105A
4 4 4
4
I
J
1058 5
5 5 5
SS
SP
1056 A
A A
A
j
I SELECTOR I
I
1054 7 7
7 7
OFFSET
I A
A
A
A
I
1052 8 8 8 8
1050
9 9 9
9
POP AX
00001
I
G30108
Figure 2-8.
Stack Operation
2-12
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Intel 80286 Specifications

General

Processor Type	Microprocessor
Clock Speed	6 MHz to 25 MHz
Transistor Count	134, 000
Addressable Memory	16 MB
Instruction Set	x86
Architecture	x86
Data Bus Width	16-bit
Address Bus Width	24-bit
Operating Modes	Real mode, Protected mode
Process Technology	1.5 µm
Voltage	5V
Introduced	1982
Package	68-pin PGA