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Intel 80286 User Manual

Intel 80286
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PROGRAMMING NUMERIC APPLICATIONS
Table
2-1.
Data
Transfer
Instructions
Real Transfers
FLD
Load real
FST Store real
FSTP Store
real and pop
FXCH
Exchange registers
Integer Transfers
FILD
Integer load
FIST
I nteger store
FISTP Integer store and pop
Packed Decimal Transfers
FBLD Packed decimal (BCD) load
FBSTP
Packed decimal (BCD) store and pop
If, however, the stack top
is
tagged special (it contains
00,
a
NaN,
or
a denormal) then the
stack
top's
significand
is
not rounded
but
is
chopped (on the right) to fit the destination. Neither
is
the exponent
converted,
but
it also
is
chopped on the right and transferred
"as
is." This preserves the value's identi-
fication as co
or
a
NaN
(exponent all ones) or a denormal (exponent all zeros) so
that
it can be properly
loaded and tagged later in the program
if
desired.
FSTP
destination
FSTP
(store real
and
pop) operates identically to
FST
except
that
the stack
is
popped following the
transfer. This
is
done by tagging the top stack element empty and then incrementing ST.
FSTP
permits
storing to a temporary real memory variable, whereas
FST
does not. Coding
FSTP
ST(O)
is
equivalent
to popping the stack with
no
data
transfer.
FXCH/
/des
tina tion
FXCH
(exchange registers) swaps the contents
of
the destination and the stack top registers.
If
the
destination
is
not coded explicitly,
ST(l)
is
used. Many 80287 instructions operate only
on
the stack
top;
FXCH
provides a simple means of effectively using these instructions on lower stack elements.
For example, the following sequence takes the square root
of
the third register from the top:
FXCH
ST(3)
FSGRT
FXCH
ST(3)
FILD
source
FILD
(integer load) converts the source memory operand from its binary integer format (word, short,
or long) to temporary real and loads (pushes) the result onto the stack. The (new) stack top
is
tagged
zero if all bits in the source were zero, and
is
tagged valid otherwise.
2-3
pcjs.org

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Intel 80286 Specifications

General IconGeneral
Processor TypeMicroprocessor
Clock Speed6 MHz to 25 MHz
Transistor Count134, 000
Addressable Memory16 MB
Instruction Setx86
Architecturex86
Data Bus Width16-bit
Address Bus Width24-bit
Operating ModesReal mode, Protected mode
Process Technology1.5 µm
Voltage5V
Introduced1982
Package68-pin PGA

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