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Intel 80286 User Manual

Intel 80286
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BASIC INSTRUCTION SET
01,
I,
I a I a
1,1,
I, I, I a 1,1,1, I a I alai' I
BEFORE
SHR
01
a
I,
I, I a I a I, I, I, I, I a I, I,
1,1
a I a I a
OF
OPERAND
CF
AFTER
SHR
BY
10
BITS
SHR
shilts
the bits
In
the register
or
memory operand
to
the right
by
the specified number
of
bit
positions.
CF
receives the
last
bit
shifted out
of
the right
of
the operand.
SHR
shifts in zeros
to
fill the vacated
bit
locations. This instruction operates on byte operands
as well as word operands.
Figure 3-7.
SHR
Dlalalalalalalalalalalalalalalal'l
c:J
I a I a I a I a I a
la
I a I a I a I a I a I a I a I a I a I a I--Q
01,
I a I a I a I, I, I, I, I a I a I a
I,
I, I a
I,
I a 1--0
D
I,
I, I,
I, I,
I, I, 1 a 1 a 1 a I,
I,
I, I,
OF
OPERAND
CF
BEFORE
SAR
WITH
A
POSITIVE
OPERAND
AFTER
SAR
WITH
A
POSITIVE
OPERAND
SHIFTED
1
BIT
iii:;r=Cn::'
SARWITH
A
NEGATIVE
OPERAND
AFTER
SAR
WITHA
NEGATIVE
OPERAND
SHIFTED
6DITS
G30108
SAR
preserves the Sign
01
the register
or
memory operand as
It
shifts the operand
to
the right the specified number
of
bit
positions.
CF
receives the last
bit
shifted out
of
the right
of
the operand. This instruction also operates on byte operands.
G30108
Figure 3-8.
SAR
3-12
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Intel 80286 Specifications

General IconGeneral
Processor TypeMicroprocessor
Clock Speed6 MHz to 25 MHz
Transistor Count134, 000
Addressable Memory16 MB
Instruction Setx86
Architecturex86
Data Bus Width16-bit
Address Bus Width24-bit
Operating ModesReal mode, Protected mode
Process Technology1.5 µm
Voltage5V
Introduced1982
Package68-pin PGA

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