Intel 8086 User Manual

8086
A.C. CHARACTERISTICS (Continued)
TIMING RESPONSES (Continued)
Symbol Parameter
8086 8086-1 8086-2
Units
Test
Min Max Min Max Min Max
Conditions
TRHAV RD Inactive to Next TCLCL-45 TCLCL-35 TCLCL-40 ns
Address Active
TCHDTL Direction Control 50 50 50 ns C
L
e
20– 100 pF
for all 8086
Active Delay
Outputs (In
(Note 1)
addition to 8086
TCHDTH Direction Control 30 30 30 ns
self-load)
Inactive Delay
(Note 1)
TCLGL GT Active Delay 0 85 0 38 0 50 ns
TCLGH GT Inactive Delay 0 85 0 45 0 50 ns
TRLRH RD Width 2TCLCL-75 2TCLCL-40 2TCLCL-50 ns
TOLOH Output Rise Time 20 20 20 ns From 0.8V to 2.0V
TOHOL Output Fall Time 12 12 12 ns From 2.0V to 0.8V
NOTES:
1. Signal at 8284A or 8288 shown for reference only.
2. Setup requirement for asynchronous signal only to guarantee recognition at next CLK.
3. Applies only to T3 and wait states.
4. Applies only to T2 state (8 ns into T3).
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Intel 8086 Specifications

General

Architecture	x86
Clock Speed	5 MHz to 10 MHz
Data Width	16-bit
Address Bus Width	20-bit
Transistor Count	29, 000
Instruction Set	x86
Package	40-pin DIP
Microarchitecture	8086
Addressable Memory	1 MB
Manufacturing Process	3 μm
Voltage	+5V
Introduced	1978
Registers	14 registers (including segment registers)