Errata
Specification Update 57
73. Disabling a Local APIC Disables Both Logical Processor APICs on a
Hyper-Threading Technology
1
Enabled Processor
Problem: Disabling a local APIC on one logical processor of a Hyper-Threading Technology
enabled processor by clearing bit 11 of the IA32_APIC_BASE MSR will effectively
disable the local APIC on the other logical processor.
Implication: Disabling a local APIC on one logical processor prevents the other logical processor
from sending or receiving interrupts. Multiprocessor Specification compliant BIOSs
and multiprocessor operating systems typically leave all local APICs enabled
preventing any end-user visible impact from this erratum.
Workaround: Do not disable the local APICs in a Hyper-Threading Technology enabled
processor.
Status: For the steppings affected, see the Summary Tables of Changes.
74. A Circuit Marginality in the 800 MHz Front Side Bus Power Save
Circuitry May Cause a System and/or Application Hang or May Result
in Incorrect Data
Problem: On a small percentage of processors, a race condition exists in the power save logic
of the internal clock circuitry controlling the movement of data to the data bus pins.
This may result in system or application hang or may cause incorrect data.
Implication: When this erratum occurs, system and/or application may hang or result in incorrect
data.
Workaround: It is possible for the BIOS to contain a workaround for this erratum. During the
BIOS POST, prior to memory initialization the BIOS must load the microcode update.
Status: For the steppings affected, see the Summary Tables of Changes.
75. Using STPCLK# and Executing Code from Very Slow Memory Could
Lead to a System Hang
Problem: The system may hang when the following conditions are met:
1. Periodic STPCLK# mechanism is enabled via the chipset
2. Hyper-Threading Technology is enabled
3. One logical processor is waiting for an event (i.e. hardware interrupt)
4. The other logical processor executes code from very slow memory such that
every code fetch is deferred long enough for the STPCLK# to be re-asserted.
Implication: If this erratum occurs, the processor will go into and out of the sleep state without
making forward progress, since the logical processor will not be able to service any
pending event. This erratum has not been observed in any commercial platform
running commercial software.
Workaround: None.
Status: For the steppings affected, see the Summary Tables of Changes.
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