12
Specification Update
AAU77
XX No Fix
2MB Page Split Lock Accesses Combined With Complex Internal Events May
Cause Unpredictable System Behavior
AAU78
XX No Fix
If the APIC timer Divide Configuration Register (Offset 03E0H) is written at the
same time that the APIC timer Current Count Register (Offset 0390H) reads 1H,
it is possible that the APIC timer will deliver two interrupts.
AAU79
XFixedTXT.PUBLIC.KEY is Not Reliable
AAU80
XFixed
8259 Virtual Wire B Mode Interrupt May Be Dropped When it Collides With
Interrupt Acknowledge Cycle From the Preceding Interrupt
AAU82
XX No Fix
The APIC Timer Current Count Register May Prematurely Read 0x0 While the
Timer is Still Running
AAU83
XX No FixSecondary PCIe Port May Not Train After A Warm Reset
AAU84
XX No FixThe PECI Bus May Be Tri-stated after System Reset
AAU85
XX No Fix
The Combination of a Page-Split Lock Access And Data Accesses That Are Split
Across Cacheline Boundaries May Lead to Processor Livelock
AAU86
XX No FixProcessor Hangs on Package C6 State Exit
AAU87
XX No FixA Synchronous SMI May be Delayed
AAU88
XX No Fix
FP Data Operand Pointer May Be Incorrectly Calculated After an FP Access
Which Wraps a 4-Gbyte Boundary in Code That Uses 32-Bit Address Size in 64-
bit Mode
AAU89
XXPlan Fix
PCI Express x16 Port Links May Fail to Dynamically Switch From 5.0GT/s to
2.5GT/s
AAU90
XX No FixPCI Express Cards May Not Train to x16 Link Width
AAU91
XX No Fix
Unexpected Graphics VID Transition During Warm Reset May Cause the System
to Hang
AAU92
XX No FixIO_SMI Indication in SMRAM State Save Area May Be Lost
AAU93
XFixedVM Entry to 64-Bit Mode May Fail if Bits 48 And 47 of Guest RIP Are Different
AAU94
XFixedVM Entry Loading an Unusable SS Might Not Set SS.B to 1
AAU95
XFixed
FSW May Be Corrupted If an x87 Store Instruction Causes a Page Fault in VMX
Non-Root Operation
AAU96
XX No Fix
Under Certain Low Temperature Conditions, Some Uncore Performance
Monitoring Events May Report Incorrect Results
AAU97
XX No FixCKE May go Low Within tRFC(min) After a PD Exit
AAU98
XX No Fix
Erratum AAU98 added to this specification Update in error; all erratum details
removed from the specification update document.
AAU99
XX No Fix
Performance Monitor Events for Hardware Prefetches Which Miss The L1 Data
Cache May be Over-Counted
AAU100
XX No FixVM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
AAU101
XFixed
Correctable and Uncorrectable Cache Errors May be Reported Until the First
Core C6 Transition
AAU102
XX No Fix
Accesses to a VMCS May Not Operate Correctly If CR0.CD is Set on Any Logical
Processor of a Core
AAU103
XX No Fix
PCIe Port’s LTSSM May Not Transition Properly in the Presence of TS1 or TS2
Ordered Sets That Have Unexpected Symbols Within those Sets
Errata (Sheet 4 of 5)
Number
Steppings
Status ERRATA
C-2 K-0
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