NVM Information Guide—ICH8/ICH9
6
Figure 1. LAN NVM Regions
To access the NVM, it is essential to correctly setup the following:
1. A valid Flash Descriptor Region must be present. Details for the Flash Descriptor
Region are contained in the ICH8/ICH9 EDS. The
FTOOL.exe utility provides the
easiest method of configuring this descriptor region. This process is described in
detail in the Intel
®
Active Management Technology OEM Bring-Up Guide.
FTOOL.exe and the Intel
®
Active Management Technology OEM Bring-Up Guide
can be obtained as part of the Intel Active Client Manager kit on ARMS
(https://platformsw.intel.com/) or by contacting your local Intel representative.
2. The GbE region must be part of the original image flashed onto the part.
3. For Intel LAN tools and drivers to work correctly, the BIOS must set the VSCC
register(s) correctly.
For the ICH9, there are two sets of VSCC registers, the upper (UVSCC) and lower
(LVSCC). Note that the LVSCC register is only used if the NVM attributes change.
For example, the use of a second flash component, a change in erase size between
segments, etc. Due to the architecture of the ICH8/ICH9, if these registers are
not set correctly, the LAN tools might not report an error message even though the
NVM contents remain unchanged. Refer to the ICH8/ICH9 EDS for more
information
4. The GbE region of the NVM must be accessible. To keep this region accessible, the
Protected Range register of the GbE LAN Memory Mapped Configuration registers
must be set to their default value of 0000 0000h. (The GbE Protected Range
registers are described in the ICH8/ICH9 EDS).
5. If you are using the 82566/82567, the ICH8/ICH9 soft strap for the GLCI
interface must be set correctly. Bit 19 of STRP0 must be set to 1b (as described in
the ICH8/ICH9 EDS). For the 82562V, this bit can be set to 0b, since it does not
use the GLCI bus.
Flash Descripto
Region 0
Region
BIOS
Region
Region
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