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ICH8/ICH9—NVM Information Guide
1.4.12 LAN Power Consumption (Word 10h)
This word is only relevant when power management is enabled.
1.4.13 Shared Initialization Control (Word 13h)
This word controls general initialization values.
Table 9. LAN Power Consumption (Word 10h)
Bit Name Default Description
15:8 LAN D0 Power
0Dh for
82566
00h for
82567
04h for
82562V
The value in this field is reflected in the PCI Power Management
Data Register of the LAN function for D0 power consumption and
dissipation (Data_Select = 0 or 4). Power is defined in 100 mW
units and includes the external logic required for the LAN function.
7:5 Reserved 000b These bits are reserved and should be set to 000b.
4:0 LAN D3 Power
00001b
for
82566
00000h
for
82567
00010b
for
82562V
The value in this field is reflected in the PCI Power Management
Data Register of the LAN function for D3 power consumption and
dissipation (Data_Select = 3 or 7). Power is defined in 100 mW
units and includes the external logic required for the LAN function.
The most significant bits in the Data Register that reflects the
power values are padded with zeros.
Table 10. Shared Initialization Control (Word 13h)
Bit Name Default Description
15:14 SIGN 10b
This is a 2-bit field indicating whether a valid NVM is present to the
MAC. If this field does not equal 10b, the MAC does not read the
NVM data and uses default values for device configuration.
00b = Invalid NVM.
01b = Invalid NVM.
10b = Valid NVM present.
11b = Invalid NVM.
13:12 Reserved 01b These bits are reserved and should be set to 01b.
11 Ext Pwr Polarity 0b
This bit defines whether the LAN Power Control (LAN_PHYPC)
signal is active high or active low. The LAN PHY Power Control
signal can be used to shut off the power rails to the LAN connected
device (only supported with the 82566/82567 PHY).
LAN PHY Power Control is generally used for Intel® Auto Connect
Battery Saver (ACBS) implementations on 82566 mobile SKUs.
0b = LAN PHY Power Control is active high.
1b = LAN PHY Power Control is active low.
Note: For the ICH9, this bit is loaded to the EXTPPOL bit in the
CTRL_EXT register.
10 Reserved 1b Reserved. Always set to 1b.
9PHY PD Enable 1b
For ICH8 designs that support an ACBS implementation using LAN
Power Control (LAN_PHYPC), this bit enables or disables PHY power
down.
0b = PHY power down feature is disabled.
1b = PHY power down feature is enabled to power down at DMoff/
D3 without Wake on LAN.
This bit is loaded to the PHY Power Down Enable bit in the
CTRL_EXT register.
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