Specification Update 39
Errata
AAZ87. FP Data Operand Pointer May Be Incorrectly Calculated after an FP
Access Which Wraps a 4-Gbyte Boundary in Code That Uses 32-Bit
Address Size in 64-bit Mode
Problem: The FP (Floating Point) Data Operand Pointer is the effective address of the operand
associated with the last non-control FP instruction executed by the processor. If an 80-
bit FP access (load or store) uses a 32-bit address size in 64-bit mode and the memory
access wraps a 4-Gbyte boundary and the FP environment is subsequently saved, the
value contained in the FP Data Operand Pointer may be incorrect.
Implication: Due to this erratum, the FP Data Operand Pointer may be incorrect. Wrapping an 80-bit
FP load around a 4-Gbyte boundary in this way is not a normal programming practice.
Intel has not observed this erratum with any commercially available software.
Workaround:If the FP Data Operand Pointer is used in a 64-bit operating system which may run
code accessing 32-bit addresses, care must be taken to ensure that no 80-bit FP
accesses are wrapped around a 4-Gbyte boundary.
Status: For the steppings affected, see the Summary Tables of Changes.
AAZ88. PCI Express Cards May Not Train to x16 Link Width
Problem: The Maximum Link Width field in the Link Capabilities register (LCAP; Bus 0; Device 1;
Function 0; offset 0xAC; bits [9:4]) may limit the width of the PCI Express link to x8,
even though the processor may actually be capable of supporting the full x16 width.
Implication: Implication: PCI Express x16 Graphics Cards used in normal operation and PCI Express
CLB (Compliance Load Board) Cards used during PCI Express Compliance mode testing
may only train to x8 link width.
Workaround:A BIOS code change has been identified and may be implemented as a workaround for
this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
AAZ89. The APIC Timer Current Count Register May Prematurely Read 0x0
While the Timer Is Still Running
Problem: The APIC Timer Current Counter Register may prematurely read 0x00000000 while the
timer is still running. This problem occurs when a core frequency or C-state transition
occurs while the APIC timer countdown is in progress.
Implication: Due to this erratum, certain software may incorrectly assess that the APIC timer
countdown is complete when it is actually still running. This erratum does not affect the
delivery of the timer interrupt.
Workaround:It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
AAZ90. IO_SMI Indication in SMRAM State Save Area May Be Lost
Problem: The IO_SMI bit (bit 0) in the IO state field at SMRAM offset 7FA4H is set to "1" by the
processor to indicate a System Management Interrupt (SMI) is either taken
immediately after a successful I/O instruction or is taken after a successful iteration of
a REP I/O instruction. Due to this erratum, the setting of the IO_SMI bit may be lost.
This may happen under a complex set of internal conditions with Intel® Hyper-
Threading Technology enabled and has not been observed with commercially available
software.
Implication: Due to this erratum, SMI handlers may not be able to identify the occurrence of I/O
SMIs.
Workaround:None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
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