Intel P4000 - 11-2010 SPECIFICATION - Page 40

Errata
40
Specification Update
AAZ91. FSW May Be Corrupted If an x87 Store Instruction Causes a Page Fault
in VMX Non-Root Operation After a PD Exit
Problem: The X87 FSW (FPU Status Word) may be corrupted if execution of a floating-point store
instruction (FST, FSTP, FIST, FISTP, FISTTP) causes a page fault in VMX non-root
operation.
Implication: This erratum may result in unexpected behavior of software that uses x87 FPU
instructions.
Workaround:None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AAZ92. CKE May go Low Within tRFC(min) After a PD Exit
Problem: After a refresh command is issued, followed by an early PD(Power Down) Entry and
Exit, the CKE (Clock Enable) signal may be asserted low prior to tRFC(min), the
Minimum Refresh Cycle timing. This additional instance of CKE being low causes the
processor not to meet the JEDEC DDR3 DRAM specification requirement (Section
4.17.4 Power-Down clarifications - Case 3).
Implication: Due to this erratum, the processor may not meet the JEDEC DDR3 DRAM specification
requirement that states: “CKE cannot be registered low twice within a tRFC(min)
window”. Intel has not observed any functional failure due to this erratum.
Workaround:None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AAZ93. Under Certain Low Temperature Conditions, Some Uncore
Performance Monitoring Events May Report Incorrect Results
Problem: Due to this erratum, under certain low operating temperatures, a small number of Last
Level Cache and external bus performance monitoring events in the uncore report
incorrect counts. This erratum may affect event codes in the ranges 00H to 0CH and
40H to 43H.
Implication: Due to this erratum, the count value for some uncore Performance Monitoring Events
may be inaccurate. The degree of under or over counting is dependent on the
occurrences of the erratum condition while the counter is active. Intel has not observed
this erratum with any commercially available software.
Workaround:None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AAZ94. VM Entry to 64-Bit Mode May Fail if Bits 48 And 47 of Guest RIP Are
Different
Problem: VM entry to 64-bit mode should allow any value for bits [47:0] of the RIP field in the
guest-state area as long as bits 63:48 are identical. Due to this erratum, such a VM
entry may fail if bit 47 of the field has a value different from that of bit 48.
Implication: It is not possible to perform VM entry to a 64-bit guest that has made a transition to a
non-canonical instruction pointer.
Workaround:It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
AAZ95. VM Entry Loading an Unusable SS Might Not Set SS.B to 1
Problem: If the unusable bit (bit 16) is 1 in the guest SS (Stack Segment) access-rights field, VM
entry should set the B bit (default stack-pointer size) in the SS (stack segment)
register to 1. Due to this erratum, VM entry may instead load SS.B from bit 14 of the
guest SS access-rights field, potentially clearing SS.B to 0.