Chapter 4 — Theory of Operation
IMAGE
CAPTURE
STATE
MACHINE
ADDR DECODE,
RD/WR CTL
DMA
BUFFER
CTL
REGs
FIFO
SD31..0
SA25..0
SCAN_IRQ
HCR_WR2*
HCR_WR5*
SDBUF_D7..0
SCAN_DREQ
Host CPU
I/F
Scanne
I/F
GPIO
REQ#, GNT#
BUS
ARBITER
DBP
COUNT
LOGIC
DQM3..0
nOE
nPWE
RDY
RD/WR
FPGA_CS
DBP_HSYNC
SOS_VSYNC
ILLUM_LASEN_RTS
SCAN_LED
SCAN_LED_LOW
TETH_DBP, SOS
TETH_PRESENT
GPIO
USER_LED<2:1>
SCAN_TRIG*
PCI
CTL
REGs
IRQ
CTL
Kypd
KEY_RET<7:0>
Scanner I/F
nWE
SPEED_RANGE_GDRD
SCAN_FLASH_EN
DOCK_TRIG*
VOL<2:0>
IMAGER_PIXCLK
BATT_FAULT_IRQ
IO MUX LOGIC
BLUR
DETECT,
EXPOSURE
SENSE
PCI/HCR_CS
Bus I/F
CK30 FPGA Block Diagram-Count Gathering for 1D Scanners
The scanner is enabled and controlled from the PXA255 through memory-
mapped registers in the FPGA and octal register U11 (see the “Using the
Scanner Interface Signal Set” table on page 76):
• SCAN_PWR_EN* is asserted low to switch 3.3V and 5V power
through high-side switches U12 and U13 to scanner connector J3. The
scan flex is used to select the voltage appropriate to the installed scanner.
The selected voltage is also routed through a loop-back on the flex to
provide the appropriate pull-up voltage (SCAN_VCC) for signals from
open-collector scanner outputs (like SCAN_TRIG*, DBP_HSYNC,
and SOS_VSYNC).
Most scanners are powered up only when scanning is commanded, but
tethered scanners are powered continuously while the CK30 is on so that
their triggers will work.
• SCAN_FLASH_EN* is asserted low to enable the scanner and/or start
its dither mirror.
• ILLUM_LASEN_RTS is asserted low to enable the laser or scanner
illumination.
• SCAN_TRIG* is set high or low depending on the scanner. This is a
general-purpose control line used for spotter beam control, scan speed
selection, scanner reset, or tethered scanner auto-detect enable,
depending on the installed scanner (See “Using the Scanner Interface
Signal Set” on page 76).
CK30 Handheld Computer Service Manual 79
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