Intermec CK30

Chapter 4 — Theory of Operation
IMAGE
CAPTURE
STATE
MACHINE
ADDR DECODE,
RD/WR CTL
DMA
BUFFER
CTL
REGs
FIFO
SD31..0
SA25..0
SCAN_IRQ
HCR_WR2*
HCR_WR5*
SDBUF_D7..0
SCAN_DREQ
Host CPU
I/F
Scanne
r
I/F
GPIO
REQ#, GNT#
BUS
ARBITER
DBP
COUNT
LOGIC
DQM3..0
nOE
nPWE
RDY
RD/WR
FPGA_CS
DBP_HSYNC
SOS_VSYNC
ILLUM_LASEN_RTS
SCAN_LED
SCAN_LED_LOW
TETH_DBP, SOS
TETH_PRESENT
GPIO
USER_LED<2:1>
SCAN_TRIG*
PCI
CTL
REGs
IRQ
CTL
Kypd
KEY_RET<7:0>
Scanner I/F
nWE
SPEED_RANGE_GDRD
SCAN_FLASH_EN
DOCK_TRIG*
VOL<2:0>
IMAGER_PIXCLK
BATT_FAULT_IRQ
IO MUX LOGIC
BLUR
DETECT,
EXPOSURE
SENSE
PCI/HCR_CS
Bus I/F
CK30 FPGA Block Diagram – 2D Imager Interface
The scanner is enabled and controlled from the PXA255 through memory-
mapped registers in the FPGA and octal register U11 (see “Using the
Scanner Interface Signal Set” on page 76):
• SCAN_PWR_EN* is asserted low to switch 3.3V power through high-
side switch U12 to scanner connector J2. This is done at boot or resume
time, and the scanner is left powered while the CK30 is on.
• SCAN_FLASH_EN* is asserted high to enable the scanner.
• ILLUM_LASEN_RTS is pulsed by a PWM circuit in the FPGA to
control the scanner illumination.
• SCAN_TRIG* is set high to enable the scanner’s aiming beam. This is
alternated with scanner illumination flashes because current imager
devices cannot handle the current draw of both being on at the same
time.
At boot time and resume time the scanner is enabled using
SCAN_PWR_EN* and SCAN_FLASH_EN*, and its configuration
registers are initialized through the system I2C bus. The imager engine
resides on the I2C bus as slave address 0x40.
Normally, when the scanner is not enabled, it is isolated from the I2C bus
by analog switch U34 so that a non-powered scanner cannot drag down
the I2C bus. Asserting SCAN_FLASH_EN* also asserts SCAN_I2C_EN,
connecting the scanner to the I2C bus.
While scanning, the scanner sends 8-bit parallel pixel data to the FPGA
over lines IMAGER_SD0-7, synced to a 13.5MHz IMAGER_PIXCLK.
CK30 Handheld Computer Service Manual 81