JVC GR-D270US

2-19(No.YF075)
!
IC6001
FA7725F
1
PGND1
2
OUT1P
3
OUT1N
4
OUT2P
5
OUT2N
6
OUT3P
7
OUT4P
8
OUT5P
9
OUT6P
10
OUT6S
11
OUT7S
12
OUT10
13
OUT11
14
OUT12
15
FB12
16
IN12-
17PGND2 18OUT9 19VCC3 20VCC1 21DGND 22ERR 23RST 24CS 25SCLK 26DATA 27VDD 28VIO9 29VREF 30IN8- 31IN8+ 32IN7+
33
IN7-
34
FB7
35
IN6C-
36
FB6C
37
IN6-
38
FB6
39
IN5-
40
FB5
41
IN4+
42
IN4-
43
FB4
44
IN3+
45
IN3-
46
FB3
47
IN2-
48
FB2
49 IN1- 50 FB1 51 FB9 52 IN9- 53 GND 54 CP 55 RT 56 VIN1 57 VIN2 58 VIN3 59 VREG 60 VIN4 61 VIN5 62 SD 63 DT 64 VCC2
F6001
NMFZ007-2R5X-K
C6003
OPEN
C6005
1
C6706
220p
C6510
0.047
C6405
0.01
C6305
0.1
C6103
220p
C6803 0.001
C6010
0.01
R6710
120k
R6712
560
R6005
30k
R6713
220k
C6705
0.01
R6105
CHRG_EVR
C6704
0.0047
R6714
4.7k
TL6001
R6709
110k
C6703
OPEN
R6708
15k
R6716
8.2k
R6715
4.7k
R6513
2.7k
C6204
220p
R6204
8.2k
R6512
47k
C6509
0.033
R6103
8.2k
R6802
4.7k
R6104 R6803
1k
C6104
680p
C6804
0.0039
C6009
0.22
C6011
1
C6105
0.01
C6008
1
D6
8
RB551V-3
L6801
NQL79GM-470X
C6
8
1
0
C6
5
1
C6
5
0
Q6103
SSM3J14T-X
D
G
S
R6106
100k
C61
0
1
R6108
36k
R6107
24k
R6718C6707
820p
R6717
18k
R6711
OPEN
C6007
0.1
C6006
0.1
R6110
C6107
0.022
BATT_+
ADP_DC
BATT_CHK
R6203C6203
0.001
TL6003
TL6002
R6006
R6007
OPEN
R6013
L6001
OPEN
L6002
OPEN
R6014
_0.5%
12k
0Ω
47µ
_0.5%
_0.5%
0Ω
3.3k
0Ω
0Ω
0Ω
0Ω
MAIN(REG)
10
TO MAIN IF(CN107)
TO MAIN IF(CN107)
TO CPU
MAIN(REG) SCHEMATIC DIAGRAM
NOTES: 1. For the destination of each signal and further line connections that are cut off from this diagram, refer to "BOARD INTERCONNECTIONS".
2. The parts with marked ( ) is not used.