JVC MX-DVB10 - Page 69

MX-DVB10
1-69
1
5
4
2
3
VCC
OUT Y
IN B
IN A
GND
TC7SH08FU-X (IC311, 312) : Timing control
14 13
12
11 10 9 8
7
6
543
2
1
1A 1B 1Y 2A 2B 2Y GND
Vcc 4B 4A 4Y 3B 3A 3Y
TC74VHC00FT-X (IC322,IC503) : Write timing control
1G 1
1A 2
1Y 3
2G 4
2A 5
2Y 6
GND 7
14 Vcc
13 4G
12 4A
11 4Y
10 3G
9 3A
8 3Y
INPUTS OUTPUTS
G
H
L
L
A
X
L
H
Y
Z
L
H
TC74VHC125FT (IC411) : Buffer
2. Truth table
X: Don't care
Z:High impedance
1.Pin layout
1. Pin layout / Block diagram
1. Pin layout / Block diagram
1 2 3 4 5 6 7 8 9
TA8409S
IN2
VCC
OUT 2
GND GND
VS
OUT 1
VR
IN1
IN1
0
1
0
1
IN2
0
0
1
1
OUT1
H
L
L
OUT2
L
H
L
MOTOR
STOP
CW/CCW
CCW/CW
BRAKE
INPUT OUTPUT MODE
TA8409S (IC802, 803) : Motor driver
1. Pin layout
2. Pin function