JVC MX-DVB10 - Page 70

MX-DVB10
1-70
1. Pin layout
(TOP VIEW)
2. Block diagram
(7)
(1)
(2)
(6)
S
C
D
R
(5)
(3)
Q
Q
PR
CK
D
CLR
1
2
3
4
8
7
6
5
Vcc
PR
CLR
Q
CK
D
Q
GND
TC7WH74FU-X (IC321) : Clock buffer
1
2
3
4
8
7
6
5
Vcc
G2
Y1
A2
G1
A1
Y2
GND
TC7W125FU-X (IC412) : Buffer
1. Pin layout
2. Block diagram
STK402-230
1
19
SUB
R2
TR3
TR1
R1
TR4
C1
R3
TR2
R4
D1
R5
TR5
TR6
R7
TR8
TR7
R6
TR9
TR10
R8
TR11
TR13
R12
TR12
R11
C2
TR14
R13 R20
TR15
TR16
R14
TR23
TR21
C3
R15
TR17
TR18
TR19
R17
TR20
R16R21
TR24
TR22
R18
R19
R9
R10
4
1
2
8
+Vcc
12
5
9
7 6 10 14 15 16 17 19 1811
CH1–VE
CH1+VE CH2+VE
CH2NF
CH2IN CH3IN
CH3NF
CH3–VE
CH3+VE
CH2–VE
13
PRE+Vcc
CH1IN
CH1NF
PRE-Vcc
BIAS
-Vcc
GND
STK402-230 (IC321) : Power amp
1. Pin layout
2. Block diagram